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Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - VHDL example design and test bench not available

AR# 32932

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Topic PCIe
Last Updated 02/14/2011
Status Active
Description

Known Issue: v1.3, v1.2 

A VHDL example design and test bench are not available in the v1.3 or v1.3 rev 2 core.

Solution

VHDL is added in the v1.4 and v2.2 (AXI-Streaming) release.

See (Xilinx Answer 33276) for other Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express known issues and release notes. 

Revision History 
02/14/2011 - Updated wording to be clearer that v1.3 will not have VHDL.
09/16/2009 - Updated for ISE Design Suite 11.3 and wrapper v1.3
08/04/2009 - Changed expected release to 11.4. 
07/08/2009 - Fixed spellcheck correction mistake. VHDL => HUDDLE 
06/24/2009 - Initial Release
Applies To

IP

  • Virtex-6 FPGA Integrated Endpoint Block for PCI Express
 
 
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