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AR# 32934

Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - How to enable 100 MHz reference clock for Gen 2 operation


Known Issue: v1.4, v1.3, v1.2

The Virtex-6 FPGA Integrated Block for PCI Express can be clocked with a 100, 125 or 250 MHz system reference clock for both Gen 1 and Gen 2 applications. See (Xilinx Answer 18329) for more information about clocking.

The current v1.4 release does not allow users to select the 100 MHz option during the CORE Generator software customization process. How, does the user enable 100 MHz in the v1.4 release.


The 100 MHz option is fully supported for Gen 2 applications, so users can lay boards out for 100 MHz even though the GUI is not supporting it yet. The v1.5 release inISE 12.1 software enablesthe option to choose 100 MHzreference clock for Gen 2 applications.

For ISE 11.5, users need to replacegtx_wrapper_v6.v/vhd file in the'<Core>/source' directorywith the relevantfile in the following linkand then follow the instructions given below:


  1. Edit the core top level Verilog or VHDL file (e.g. v6_pcie_v1_5.v/vhd) in the <Core_Name>/source directory, set REF_CLK_FREQ to '0' instead of '2' in the generic list. The name of the file will be the same as the generated core name entered during the customization process.
  2. For simulation of Verilog designs make the following changes:
    1. Editsimulation/functional/board.v:
      • At the top of the file change theparameter REF_CLK_FREQ to 0 instead of 2. This is the parameter defined as:"parameter REF_CLK_FREQ 2".
      • In the instantiation ofthexilinx_pcie_2_0_rport module instance change REF_CLK_FREQ to'0'.
    2. Editsimulation/functional/board_common.v and changeSYS_CLK_COR_HALF_CLK_PERIOD to 5000 from 2000.
  3. For simulation of VHDL designs edit<Core>/simulation/functional/board.vhdand make these changes:
    • In generic map for entity board : REF_CLK_FREQ : integer := 0;
    • Generic map for instance CLK_GEN_RP of sys_clk_gen : CLK_FREQ => 100
    • Generic map for instance CLK_GEN_EP of sys_clk_gen_ds : CLK_FREQ => 100
  4. Change the following in the XCF file:
    • TIMESPEC "TS_CLK_125" = PERIOD "CLK_125" TS_SYSCLK*1.25;
    • TIMESPEC "TS_CLK_250" = PERIOD "CLK_250" TS_SYSCLK*2.5 HIGH 50 %;
    • If the Design is a x1 Gen2, also update TIMESPEC "TS_USR_CLK" = PERIOD CLK_USR TS_SYSCLK/1.6 HIGH 50 %;
  5. Change the following in the UCF:
    • TIMESPEC "TS_CLK_125" = PERIOD "CLK_125" TS_SYSCLK*1.25 HIGH 50 % <>;
    • TIMESPEC "TS_CLK_250" = PERIOD "CLK_250" TS_SYSCLK*2.5 HIGH 50 % <>;
    • If the Design is a x1 Gen2, also update TIMESPEC "TS_USER_CLK" = PERIOD "CLK_USER_CLK" TS_SYSCLK/1.6 HIGH 50 % <>;
    • If the Design is a x8 Gen2, also update TIMESPEC "TS_CLK_500" = PERIOD "CLK_500" TS_SYSCLK*5 HIGH 50 % PRIORITY 1;

Revision History
3/22/2010- Added step-by-step instructions to enable 100 MHz for Gen2.
2/22/2010 - Removed the 250 MHz only restriction and added support for Gen 2 at 100 MHz.
12/02/2009 - Updated for 11.4
09/16/2009 - Updated for ISE Design Suite 11.3 and wrapper v1.3
06/24/2009 - Initial Release

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AR# 32934
Date Created 06/11/2009
Last Updated 05/22/2012
Status Active
Type Known Issues
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • ISE Design Suite - 11.4
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )