AR #32971 - 11.x XST - "ERROR:HDLCompiler:40 - <file>.vhd Line xx: <name> is not a component"
11.x XST - "ERROR:HDLCompiler:40 - <file>.vhd Line xx: <name> is not a component"
| AR# | 32971 |
| Part | SW-XST |
| Last Modified | 2009-06-23 00:00:00.0 |
| Status | Active |
| Keywords | XST, Spartan-6, Virtex-6, S6, V6, HDLCompiler:40 |
Description
Keywords: XST, Spartan-6, Virtex-6, S6, V6, HDLCompiler:40
I have a design where the component and signal have the same name. I get the following error in XST when targeting Virtex-6/Spartan-6 devices, but do not have any issues when I target older devices. Why?
"ERROR:HDLCompiler:40 - "<file>.vhd" Line xx: <name> is not a component"
Example Code:
File: ex_0001.vhd
Compilation Library: work
library ieee;
use ieee.std_logic_1164.all;
package my_pack_0001 is
component my_name is
port(in_port : in std_logic;
out_port: out std_logic);
end component;
end package;
-----------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.my_pack_0001.all;
entity ex_0001 is
port(in_port : in std_logic;
out_port: out std_logic);
end ex_0001;
architecture beh of ex_0001 is
signal my_name : std_logic;
begin
my_name <= in_port;
my_inst : my_name port map(in_port =>my_name, -- Note: Error points here
out_port=>out_port);
end;
Solution
In 11.2 XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families. For more information on this change, please refer to (Xilinx Answer 32927)This is not a VHDL LRM compliant code. To solve the problem, you have to rename a signal or a component.
For example, in the above code you can edit the source to:
library ieee;
use ieee.std_logic_1164.all;
package my_pack_0001 is
component my_name is
port(in_port : in std_logic;
out_port: out std_logic);
end component;
end package;
-----------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.my_pack_0001.all;
entity ex_0001 is
port(in_port : in std_logic;
out_port: out std_logic);
end ex_0001;
architecture beh of ex_0001 is
signal my_name : std_logic;
begin
my_name <= in_port;
my_inst : my_name port map(in_port =>my_name, -- Note: Error points here
out_port=>out_port);
end;
In the above code rename my_name to my_name_signal