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AR# 32972

Virtex-5, Virtex-6, and Spartan-6 GTX/GTP - Far-End PCS Loopback data errors


In all GTP and GTX High Speed Transceivers, it is possible to see either data or disparity errors in received data when clock correction is enabled. This Answer Record discusses why this can occur and what to do to work around it.


In Far-End PCS Loopback, all of the circuits up to the elastic buffer are still used prior to the data being looped back and re-transmitted.

If comma alignment is not disabled for non-8b10b encoded data, it is possible that the random data is acknowledged as an alignment character, causing realignment and potentially losing data in the process. This can be seen in SONET-like applications, so if this is a concern, setting ENMCOMMADET and ENPCOMMADET = 1'b0 will disable comma alignment.

If clock correction is not disabled, the link partner may detect disparity errors if the clock correction character is non-neutral (containing an equal number of 1's and 0's) when clock correction sequences are received and removed/added, since all 8b10b data will have its disparity maintained upon re-transmission. To work around this situation, the near- and far-end reference clocks must be sourced from the same oscillator and the CLK_CORRECT_USE_x attribute set to FALSE.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33475 Virtex-6 FPGA GTX Transceiver - Known Issues and Answer Record List N/A N/A
AR# 32972
Date Created 06/16/2009
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LXT
  • Virtex-5 FXT
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  • Virtex-5 SXT
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  • Virtex-6 CXT
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  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2