AR #32974 - 11.2 XST - "ERROR:HDLCompiler:940 - "<file>.vhd" Line xx: Unmatched pragma translate/synthesis_off pragma found"
11.2 XST - "ERROR:HDLCompiler:940 - "<file>.vhd" Line xx: Unmatched pragma translate/synthesis_off pragma found"
| AR# | 32974 |
| Part | SW-XST |
| Last Modified | 2009-06-23 00:00:00.0 |
| Status | Active |
| Keywords | XST, Spartan-6, Virtex-6, S6, V6, 11.2 , Parser, HDLCompiler:940 |
Description
Keywords: XST, Spartan-6, Virtex-6, S6, V6, 11.2 , Parser, HDLCompiler:940
I am retargeting my design with Virtex-6/Spartan-6 and it errors out in Synthesis, with the following error. This design passes XST synthesis when I target older devices. Why?
ERROR:HDLCompiler:940 - " ex_0005.vhd" Line 16: Unmatched pragma translate/synthesis_off pragma found. A matched pair of translate_off and translate_on directives with same keywords is required.
VHDL Example code
library ieee;
use ieee.std_logic_1164.all;
entity ex_0005 is
port(clk: in std_logic;
d : in std_logic;
q : out std_logic);
end ex_0005;
architecture beh of ex_0005 is
begin
process (clk)
begin
if (clk'event and clk='1') then
q <= d;
-- pragma translate_off
q <= not (d);
-- translate_on
end if;
end process;
end;
Verilog example code
File: ex_0005_v.v
Compilation Library: work
module ex_0005_v (clk, d, q);
input clk, d;
output q;
reg q;
always @(posedge clk)
begin
q <= d;
// pragma translate_off -- Note: Error points here
q <= not (d);
// translate_on
end
endmodule
Solution
11.2 XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families. For more information on this change, please refer to (Xilinx Answer 32927)translate_off and translate_on directives must have the same keywords when design is compiled with XST for Virtex-6 and Spartan-6 families. The following keywords are supported: synthesis, synopsys, pragma, exemplar, verific. You may use translate_off/_on directives without keywords.
To solve this issue, use the same keywords for translate_off/_on directives.
For example, in the above code you can edit the source to:
library ieee;
use ieee.std_logic_1164.all;
entity ex_0005 is
port(clk: in std_logic;
d : in std_logic;
q : out std_logic);
end ex_0005;
architecture beh of ex_0005 is
begin
process (clk)
begin
if (clk'event and clk='1') then
q <= d;
-- pragma translate_off -- Note: Error points here
q <= not (d);
-- pragma translate_on
end if;
end process;
end;
File: ex_0005_v.v
Compilation Library: work
module ex_0005_v (clk, d, q);
input clk, d;
output q;
reg q;
always @(posedge clk)
begin
q <= d;
// pragma translate_off -- Note: Error points here
q <= not (d);
// pragma translate_on
end
endmodule