AR #32975 - 11.2 XST - " ERROR:HDLCompiler:410 - "<file>.vhd" Line xx: Expression has x elements; expected y"
11.2 XST - " ERROR:HDLCompiler:410 - "<file>.vhd" Line xx: Expression has x elements; expected y"
| AR# | 32975 |
| Part | SW-XST |
| Last Modified | 2009-06-23 00:00:00.0 |
| Status | Active |
| Keywords | XST, Spartan-6, Virtex-6, S6, V6, 11.2 , Parser, HDLCompiler:410 |
Description
Keywords: XST, Spartan-6, Virtex-6, S6, V6, 11.2 , Parser, HDLCompiler:410
I get the following error when I target Virtex-6/Spartan-6 devices, but the same code passes when targeting older devices with a warning. How do I resolves this?
ERROR:HDLCompiler:410 - "<file>.vhd" Line xx: Expression has x elements ; expected y
Example code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ex_0006 is
port(a,b : in unsigned (7 downto 0);
res : out unsigned (8 downto 0));
end ex_0006;
architecture beh of ex_0006 is
begin
res <= a + b; -- Note: Error points here
end beh;
Solution
The above code is not a VHDL LRM compliant. To resolve the error, you have to use resize function from numeric_std package to align the left and right side of assignment.library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ex_0006 is
port(a,b : in unsigned (7 downto 0);
res : out unsigned (8 downto 0));
end ex_0006;
architecture beh of ex_0006 is
begin
res <= resize(a,9) + resize(b,9); -- Note: Error points here
end beh;
11.2 XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families. For more information on this change, please refer to (Xilinx Answer 32927)