I receive the following error when I target Virtex-6/Spartan-6 devices, but the same code passes with a warning when targeting older devices.
How do I resolves this?
The above code is not VHDL LRM compliant.
To resolve the error, use the resize function from the numeric_std package to align the left and right side of assignment.
ISE Design Suite 11.2 XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families.
For more information on this change, please refer to (Xilinx Answer 32927)