AR #32976 - 11.x XST - "ERROR:HDLCompiler:69 - "<file>.vhd" Line xx:: <xyz> is not declared"
11.x XST - "ERROR:HDLCompiler:69 - "<file>.vhd" Line xx:: <xyz> is not declared"
| AR# | 32976 |
| Part | SW-XST |
| Last Modified | 2009-06-23 00:00:00.0 |
| Status | Active |
| Keywords | XST, Spartan-6, Virtex-6, S6, V6, 11.2 , Parser, HDLCompiler:69, HDLCompiler:461 |
Description
Keywords: XST, Spartan-6, Virtex-6, S6, V6, 11.2 , Parser, HDLCompiler:69, HDLCompiler:461
I get the following error in XST when targeting Virtex-6/Spartan-6 devices, but do not have any issues when I target older devices. why?
ERROR:HDLCompiler:69 - "<file>.vhd" Line xx:: <xyz> is not declared.
ERROR:HDLCompiler:461 - "<file>.vhd" Line xx:: If you are trying to directly instantiate a design entity, please use expanded name.
Example code:
library ieee;
use ieee.std_logic_1164.all;
entity subb_0007 is
port(in_port : in std_logic;
out_port: out std_logic);
end subb_0007;
architecture beh of subb_0007 is
begin
out_port <= in_port;
end;
-----------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ex_0007 is
port(in_port : in std_logic;
out_port: out std_logic);
end ex_0007;
architecture beh of ex_0007 is
begin
my_name : entity subb_0007 port map(in_port =>in_port,
out_port=>out_port);
end;
Solution
The above example attempts to use direct instantiation, but the subb_0007 entity is used without a library name. This is not a VHDL LRM compliant code. To solve the problem you have to use expanded name for the instantiations.For example:- work.subb_0007 is used to fix the above code.
library ieee;
use ieee.std_logic_1164.all;
entity subb_0007 is
port(in_port : in std_logic;
out_port: out std_logic);
end subb_0007;
architecture beh of subb_0007 is
begin
out_port <= in_port;
end;
-----------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ex_0007 is
port(in_port : in std_logic;
out_port: out std_logic);
end ex_0007;
architecture beh of ex_0007 is
begin
my_name : entity work.subb_0007 port map(in_port =>in_port, -- Note: Error points here
out_port=>out_port);
end;
In 11.2 XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families. For more information on this change please refer (Xilinx Answer 32927)