AR #32981 - 11.2 XST - "ERROR:HDLCompiler:377 - "<file>.vhd" Line xx: Entity port in_port does not match with type std_logic_vector of component port"

AR#	32981
Part	SW-XST
Last Modified	2009-06-24 00:00:00.0
Status	Active
Keywords	XST, Spartan-6, Virtex-6, 11.2 , Parser, HDLCompiler:377

Solution

In the example above, the subb_0014 sub block has 2 ports of type bit_vector. The component subb_0014 declared in the ex_0014 has 2 ports of a different type: std_logic_vector. This is not a VHDL LRM compliant code.

To solve this issue, align the entity and component port types.


library ieee;
use ieee.std_logic_1164.all;

entity subb_0014 is
port(in_port : in std_logic_vector(3 downto 0); -- Note: Info points here
out_port: out std_logic_vector(3 downto 0)); -- Note: Info points here
end subb_0014;

architecture beh of subb_0014 is
begin
out_port <= in_port;
end;

------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity ex_0014 is
port(in_port : in std_logic_vector(3 downto 0);
out_port: out std_logic_vector(3 downto 0));
end ex_0014;

architecture beh of ex_0014 is

component subb_0014 is
port(in_port : in std_logic_vector(3 downto 0); -- Note: Error points here
out_port: out std_logic_vector(3 downto 0)); -- Note: Error points here
end component;

begin
inst : subb_0014 port map(in_port => in_port, out_port=>out_port);
end;



In 11.2, XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families. For more information on this change, see(Xilinx Answer 32927).