AR #32983 - 11.2 XST - "ERROR:HDLCompiler:607 - "<file>.vhd" Line xx: Multiple declarations of my_const included via multiple use clauses; none are made directly visible"
11.2 XST - "ERROR:HDLCompiler:607 - "<file>.vhd" Line xx: Multiple declarations of my_const included via multiple use clauses; none are made directly visible"
| AR# | 32983 |
| Part | SW-XST |
| Last Modified | 2009-06-24 00:00:00.0 |
| Status | Active |
| Keywords | XST, Spartan-6, Virtex-6, 11.2 , Parser, HDLCompiler:607, Multiple declarations |
Description
Keywords: XST, Spartan-6, Virtex-6, 11.2 , Parser, HDLCompiler:607, Multiple declarations
The following error occurs in XST when I target Virtex-6 or Spartan-6 devices, but I do not have any issues when I target older devices. Why?
ERROR:HDLCompiler:607 -"<file>.vhd" Line xx: Multiple declarations of my_const included via multiple use clauses; none are made directly visible
"<file>.vhd" Line aa. my_const is declared here
"<file>.vhd" Line bb Another match is here
library ieee;
use ieee.std_logic_1164.all;
package pack_0017_1 is
constant my_const: std_logic := '1';
end package;
-----------------------------------
library ieee;
use ieee.std_logic_1164.all;
package pack_0017_2 is
constant my_const: std_logic:= '0';
end package;
-----------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.pack_0017_1.all;
use work.pack_0017_2.all;
entity ex_0017 is
port(in_port : in std_logic;
out_port: out std_logic);
end ex_0017;
architecture beh of ex_0017 is
begin
out_port <= in_port and my_const; -- Note: Error points here
end
Solution
In the above example code, my_const constant is declared in two different packages: pack_0017_1 and pack_0017_2. Both packages are used in the ex_0017 block via use clause. This is not a VHDL LRM compliant code.There are two ways this problem can be solved:
- Use only one package via use clause.
- Explicitly specify the constant and the package where it comes from as shown below for my_const from package pack_0017_1.
library ieee;
use ieee.std_logic_1164.all;
package pack_0017_1 is
constant my_const: std_logic := '1';
end package;
-----------------------------------
library ieee;
use ieee.std_logic_1164.all;
package pack_0017_2 is
constant my_const: std_logic:= '0';
end package;
-----------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ex_0017 is
port(in_port : in std_logic;
out_port: out std_logic);
end ex_0017;
architecture beh of ex_0017 is
begin
out_port <= in_port and work.pack_0017_1.my_const;
end;
In 11.2 XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families. For more information on this change please refer (Xilinx Answer 32927)