AR #32984 - 11.x XST - "ERROR:HDLCompiler:16 - "<file>.vhd" Line xx : <width> cannot be used within its own interface list. Please verify that you don't use this object for the definition of other interface components."
11.x XST - "ERROR:HDLCompiler:16 - "<file>.vhd" Line xx : <width> cannot be used within its own interface list. Please verify that you don't use this object for the definition of other interface components."
| AR# | 32984 |
| Part | SW-XST |
| Last Modified | 2009-06-24 00:00:00.0 |
| Status | Active |
| Keywords | XST, Spartan-6, Virtex-6, 11.2 , Parser, HDLCompiler:16 |
Description
Keywords: XST, Spartan-6, Virtex-6, 11.2 , Parser, HDLCompiler:16
The following error occurs in XST when I target Virtex-6 or Spartan-6 devices, but I do not have any issues targeting older devices. Why?
ERROR:HDLCompiler:16 - "<file>.vhd" Line xx: <width> cannot be used within its own interface list. Please verify that you don't use this object for the definition of other interface components.
Example code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ex_0018 is
port(in_port : in std_logic_vector(7 downto 0);
out_port: out std_logic_vector(7 downto 0));
end ex_0018;
architecture beh of ex_0018 is
procedure add_0018 (
constant width: integer:=8; -- Note: Error point here
signal inp: in std_logic_vector(width-1 downto 0);
signal outp: out std_logic_vector(width-1 downto 0)) is
begin
outp <= inp + 5;
end add_0018;
begin
add_0018(inp=>in_port, outp=>out_port);
end;
Solution
In the above code, the constant width is declared and used in the add_0018 procedure interface list. This is not a VHDL LRM compliant code. To solve this issue, declare the constant width outside the procedure boundaries as shown below.library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ex_0018 is
port(in_port : in std_logic_vector(7 downto 0);
out_port: out std_logic_vector(7 downto 0));
end ex_0018;
architecture beh of ex_0018 is
constant width: integer:=8;
procedure add_0018 (
signal inp: in std_logic_vector(width-1 downto 0);
signal outp: out std_logic_vector(width-1 downto 0)) is
begin
outp <= inp + 5;
end add_0018;
begin
add_0018(inp=>in_port, outp=>out_port);
end;
In 11.2, XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families. For more information on this change, see (Xilinx Answer 32927).