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AR# 32996

Virtex-5/Virtex-6 GTP/GTX and Spartan-6 GTP Transceiver Wizard - Timing not met on implemented example design


When RXRECCLK is used to generate RXUSRCLK, it is possible that timing will not be met upon implementation. This Answer Record discusses the issue and how to work around it.


When RXRECCLK is used to generate RXUSRCLK or multiple reference clocks are used, it is possible for the clock supplying the automatically generated ChipScope ILA Core to fail timing. Currently, the only method for working around this problem is to remove the automatically generated ChipScope cores. The simplest way to do this is to set the EXAMPLE_USE_CHIPSCOPE parameter to 0.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33475 Virtex-6 FPGA GTX Transceiver - Known Issues and Answer Record List N/A N/A
AR# 32996
Date Created 06/17/2009
Last Updated 05/19/2012
Status Active
Type Known Issues
  • Spartan-6 LXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2