11.2 XST - ERROR:HDLCompiler:56 - <file>.vhd Line xx: <name> is not a signal.
Description
Keywords: XST, Spartan-6, Virtex-6, S6, V6
I have a design where I declared an output port the same name as one of my processes . I get the following error with Virtex-6/Spartan-6, but do not have any issues with any of the older devices. Why?
ERROR:HDLCompiler:56 - <file>.vhd Line xx: <name> is not a signal.
The following example results in an error; notice that the name of the port and process are both q:
library ieee;
use ieee.std_logic_1164.all;
entity ex_0004 is
port(clk: in std_logic;
d : in std_logic_vector(3 downto 0);
q : out std_logic_vector(3 downto 0));
end ex_0004;
architecture beh of ex_0004 is
begin
genloop: for i in 0 to 3 generate
q: process (clk)
begin
if (clk'event and clk='1') then
q <= d; -- Note: Error points here
end if;
end process;
end generate;
end;
Solution
11.2 XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families. For more information on this change, please refer to (Xilinx Answer 32927)The above code is not VHDL LRM compliant. To solve this, simply change the name of either the port or the process.
For example, in the above code you can edit the source to:
library ieee;
use ieee.std_logic_1164.all;
entity ex_0004 is
port(clk: in std_logic;
d : in std_logic_vector(3 downto 0);
q : out std_logic_vector(3 downto 0));
end ex_0004;
architecture beh of ex_0004 is
begin
genloop: for i in 0 to 3 generate
q_label: process (clk)
begin
if (clk'event and clk='1') then
q <= d; -- Note: Error points here
end if;
end process;
end generate;
end;