Description
I see the following errors during BitGen with my Spartan-6 design. The design was routed using the Spartan-6 beta software, but now fails in BitGen after upgrading to ISE version 11.2. What is illegal about the routing?
ERROR:Bitgen:306 - Illegal routing for signal
<io_ddr_opposite_dff_a.top_pins_group.clk_in1.my_bufg_o>. The routing for
ILOGIC_X27Y115.CLK0 and OLOGIC_X27Y115.CLK0 conflicts with the routing for
OLOGIC_X27Y115.CLK1.
Solution
;This problem occurred in the beta version of the tools due to a device modeling problem that caused the router to create a configuration that would not work in hardware. The root cause of this problem has been fixed for ISE version 11.2 and the Bitgen:306 error was created to catch designs routed in previous beta versions. This error can be avoided by rerunning PAR so that the design is rerouted with the fixes.
NOTE: If this error is seen with a design that was routed in ISE version 11.2 or later, please report this to Xilinx via a WebCase.
http://www.xilinx.com/support/clearexpress/websupport.htm