;This problem occurred in the beta version of the tools due to a device modeling problem that caused the router to create a configuration that would not work in hardware. The root cause of this problem has been fixed for ISE version 11.2 and the Bitgen:306 error was created to catch designs routed in previous beta versions. This error can be avoided by rerunning PAR so that the design is rerouted with the fixes.
NOTE: If this error is seen with a design that was routed in ISE version 11.2 or later, please report this to Xilinx via a WebCase.
http://www.xilinx.com/support/clearexpress/websupport.htm