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AR# 33007

11.1 Timing, Virtex-4 - "WARNING:Timing:3327 - Timing Constraint" - Component Switching Limit is limited by DLL portion of the DCM when both DLL and DFS DCM outputs are used


Keywords: Timing, DCM, Timing Analysis, DLL, DFS, Virtex-4

In Virtex-4 designs, using both the DLL and DFS outputs of a DCM show the following warning (depending on clock frequency):

"WARNING:Timing:3327 - Timing Constraint *** fails the minimum period check for the input clock because the period constraint value *** is less than the minimum internal period limit of ***. Please increase the period of the constraint to remove this timing failure."

When is this going to be fixed?


This is expected behavior of the timing analysis. If both DLL and DFS outputs are used, follow the more restrictive specifications. The CLKIN_FREQ_FX_LF/HF_MIN/MAX should always be used to determine DFS_FREQUENCY_MODE (no matter whether or not DLL outputs are also used).

AR# 33007
Date Created 06/25/2009
Last Updated 06/26/2009
Status Active
Type General Article