11.2 Virtex-6 Place - Designs with very low utilization may have very poor QOR
Description
My design is very small, but it failed to route successfully. When I examined the placement in FPGA Editor, I can see that the placement is very congested. Is this a known problem?
Solution
While there have been some improvements for ISE 11.2 since the beta release for Virtex-6, there are still some issues with the quality of placement results for very low utilization designs. Some special placement algorithms are used to handle such designs and this sometimes causes problems. In one case, a single module was implemented with an Area Group Range that restricted the placement to a small but sufficient area of the device. The placement results for this implementation were very poor with many timing errors. When the low utilization algorithms were disabled, the timing results improved dramatically.
The following variable can be tried in the case where the QOR are suspect for a low utilization design:
Linux
setenv PAR_USE_LOWUTILHEUR 0
Windows
SET PAR_USE_LOWUTILHEUR=0
For general information about setting ISE environment variables, see (Xilinx Answer 11630).
Applies To
Devices
- Virtex-6 CXT
- Virtex-6 HXT
- Virtex-6 LX
- Virtex-6 LXT
- Virtex-6 SXT
Design Tools
- ISE Design Suite - 11.2
- ISE Design Suite - 11.3
- ISE Design Suite - 11.4
- ISE Design Suite - 11.5
- ISE Design Suite - 12.1
- ISE Design Suite - 12.2