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AR# 33023

12.4/13.4/14.7 Spartan-6 Place - Clock Placer creates unroutable BUFG-->BUFG cascade

Description

My design has a BUFG-->BUFG cascade that ends up being unroutable. 

What are the routing restrictions involved that prevent this connection from routing? 

Why did the Placer fail to choose a routable placement?

Solution


There is a routing restriction in Spartan-6 devices that only the eight BUFGs from the "upper" column of BUFG sites can drive non-clock loads. 

The BUFG cascade load qualifies as a non-clock load.  

This problem can be worked around by constraining the BUFG driver to an upper row site.

The valid site names for the upper column of BUFG sites can be identified by examining the available sites in FPGA Editor.

The following commands can be used to zoom into the BUFG sites: 

  • select site BUFG* 
  • zoom selection 

 Choose an available BUFG site from the upper group and add a LOC constraint to the UCF file:  

INST "bufg_symbol_name" LOC = BUFGMUX_X3Y8;

AR# 33023
Date Created 06/22/2009
Last Updated 09/16/2014
Status Active
Type General Article
Devices
  • Spartan-6
  • Spartan-6Q
Tools
  • ISE Design Suite - 14
  • ISE Design Suite - 13
  • ISE Design Suite - 12