AR #33038 - 11.x XST - "WARNING:HDLCompiler:924 - " <file name" Line ##: Attribute target identifier state not found in this scope"

AR#	33038
Part	SW-XST
Last Modified	2009-06-24 00:00:00.0
Status	Active
Keywords	HDLCompiler:924, Virtex-6, Spartan-6, metacomments

Solution

In 11.2, XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families. For more information on this change, see (Xilinx Answer 32927).

With the introduction of Verilog-2001, Verilog attributes became the preferable method to apply design constraint. XST still supports Verilog synthesis metacomments, however, for metacomments to work in Virtex-6 or Spartan-6 designs there are limitations, as follows:

If metacomment is applied to:
A signal and metacomment is located
-before the module description, then both XST for older devices and XST for Virtex-6 and Spartan-6 families ignore the attribute.
-inside the module description, then both XST for older devices and XST for Virtex-6 and Spartan-6 families takes this metacomment into account.
-after the module description, then XST for older devices takes this metacomment into account while XST for Virtex-6 and Spartan-6 families ignores it.
-a module, then regardless of the metacomment location, XST for older devices and XST for Virtex-6 and Spartan-6 families take it into account.

In the following example, fsm_extract constraint is applied to the state signal. The constraint is located after the module description.

File: ex_0016_v.v
Compilation Library: work

module ex_0016_v (clk, reset, x1, outp);
input clk, reset, x1;
output outp;
reg outp;
reg [1:0] state;

parameter s1 = 2'b00; parameter s2 = 2'b01;
parameter s3 = 2'b10; parameter s4 = 2'b11;

initial begin
state = 2'b00;
end

always@(posedge clk or posedge reset)
begin
if (reset)
begin state <= s1; outp <= 1'b1; end
else
begin
case (state)
s1: begin
if (x1==1'b1)
begin
state <= s2;
outp <= 1'b1;
end
else
begin
state <= s3;
outp <= 1'b0;
end
end
s2: begin state <= s4; outp <= 1'b1; end
s3: begin state <= s4; outp <= 1'b0; end
s4: begin state <= s1; outp <= 1'b0; end
endcase
end
end

endmodule

// synthesis attribute fsm_extract of state is "no" // NOTE: Warning points here.

XST for older devices accepts the metacomment and does not infer a state machine.

Set property "fsm_extract = no" for signal <state>.


XST for Virtex-6 and Spartan-6 families ignores the metacomment applied on a signal and extracts the state machine.

WARNING:HDLCompiler:924 - "ex_59_1_0.v" Line 42: Attribute target identifier state not found in this scope
...
Found finite state machine <FSM_0> for signal <state>.


To solve this problem, the metacomment must be placed inside the module description.

File: ex_0016_v.v
Compilation Library: work

module ex_0016_v (clk, reset, x1, outp);
input clk, reset, x1;
output outp;
reg outp;
reg [1:0] state;

parameter s1 = 2'b00; parameter s2 = 2'b01;
parameter s3 = 2'b10; parameter s4 = 2'b11;

initial begin
state = 2'b00;
end

// synthesis attribute fsm_extract of state is "no"

always@(posedge clk or posedge reset)
begin
if (reset)
begin state <= s1; outp <= 1'b1; end
else
begin
case (state)
s1: begin
if (x1==1'b1)
begin
state <= s2;
outp <= 1'b1;
end
else
begin
state <= s3;
outp <= 1'b0;
end
end
s2: begin state <= s4; outp <= 1'b1; end
s3: begin state <= s4; outp <= 1'b0; end
s4: begin state <= s1; outp <= 1'b0; end
endcase
end
end

endmodule

Xilinx recommends that you not use metcomments. Rather, you should follow the Verilog 2001construct to pass attributes.