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AR# 33048

Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - In x8 Gen 2 Mode, on Block Interface cfg_interrupt_n Asserts for Extra Cycles After cfg_interrupt_rdy_n

Description


Known Issue: v1.2



When operating in x8 Gen 2 Mode, the 128-bit wrapper asserted the cfg_interrupt_n input to the block for extra clock cycles after the block asserted cfg_interrupt_rdy_n output.

Solution


This issue is fixed in the v1.2.1 patch. This patch is available from (Xilinx Answer 32742)



For other Virtex-6 Integrated Block Wrapper v1.2 and v1.2.1 for PCI Express Known Issues and Release Notes, see (Xilinx Answer 32742).



Revision History

06/25/2009 - Initial Release
AR# 33048
Date Created 06/25/2009
Last Updated 08/06/2010
Status Active
Type ??????
IP
  • Virtex-6 FPGA Integrated Endpoint Block for PCI Express