We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33049

Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - In x8 Gen 2 Mode, Transmitter Lockup due to De-assertion of trn_tsrc_rdy_n Along with Assertion of trn_teof_n Concurrent with Internally Generated Transaction


Known Issue: v1.2 
When operating in x8 Gen 2 mode, the transmit interface may lock-up on de-assertion of trn_tsrc_rdy_n along with assertion of trn_teof_n. This could happen if at the same time the Integrated Block for PCI Express is internally generating a transaction.


This issue is fixed in the v1.2.1 patch. This patch is available from (Xilinx Answer 32742) 
For other Virtex-6 Integrated Block Wrapper v1.2 and v1.2.1 for PCI Express Known Issues and Release Notes, see (Xilinx Answer 32742)
Revision History 
06/25/2009 - Initial Release
AR# 33049
Date Created 06/25/2009
Last Updated 08/26/2013
Status Active
Type General Article
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )