UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33107

LogiCORE Ethernet AVB Endpoint v2.1 - Timing failures seen in some Spartan 3/3A/3ADSP implementations

Description

When targeting the LogiCORE Ethernet AVB Endpoint v2.1 core to Spartan-3, Spartan-3A, and Spartan-3ADSP devices, timing failures are seen on some implementations.

Solution

Often re-running MAP and PAR with a small change will allow the design to meet timing. These changes include a small change in the customer design, a different seed, or a different implementation option.

New ISE tools such as smartexplorer should also help to achieve timing closure.

Alternatively, the following UCF constraint can be used to help guide the tools. The failing path that has been seen is from the output of a 32-bit comparator (implemented in a carry chain) to the flip-flop that registers the comparator result. In failing testcases the tools are placing this flip-flop away from the carry chain. The UCF constraints shown below implement RLOCs to force the flip-flop placement to be near the carry chain.

# Guidelines for optimal placement of critical timing logic

#----------------------------------------------------------

INST "*top/rtc_inst/Mcompar_pulse16k_cmp_lt0000_cy<31>" RLOC = X0Y0;

INST "*top/rtc_inst/pulse16k" RLOC = X2Y0;

AR# 33107
Date Created 07/08/2009
Last Updated 12/15/2012
Status Active
Type General Article