UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33110

LogiCORE Ethernet Statistics v3.2 - Change to testbench needed to run Spartan-6 Example Design Timing Simulation

Description

When running the Spartan-6 LogiCORE Ethernet Statistics v3.2 Example Design Timing Simulation, a change is required to the demo_tb for Spartan-6 to enable timing simulations to run correctly. The DLY value needs to be changed to adjust the clock/data relationship. Since this core is never expected to be connected up to I/O's (it is designed for internal connections to MAC and MAC Host I/F), this interface would never have these issues when actually connected to an internal MAC.

Solution

The changes to be made to the demonstration testbench files: 

 

1. Search for the string 'DLY". 

2. Then edit to match the following text: 

 

VHDL: 

-- To provide setup and hold times on inputs 

constant DLY : time := 7 ns; 

 

Verilog: 

// To provide setup and hold times on inputs 

parameter dly = 7000; // 7 ns

AR# 33110
Date Created 07/08/2009
Last Updated 05/23/2014
Status Archive
Type General Article