| AR# | 33113 |
| Part | SW-Timing Analyzer/TRCE |
| Last Modified | 2009-08-06 00:00:00.0 |
| Status | Active |
| Keywords | Timing, Analyzer, Autogenerated, incorrect, Virtex5, Virtex-5 |
Keywords: Timing, Analyzer, Autogenerated, incorrect, Virtex5, Virtex-5
When trying to analyze the design against Auto-generated timing constraints for a Virtex-5 design, I find that the clk to pad value in the data sheet report is incorrectly reported.
Is this a known issue?