We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33118

11.x - How do I run simulation with Xilinx SecureIP in ModelSim without a Verilog license?


I am using HardIP models (PPC, GT, TEMAC) in my design and I have a VHDL only license for ModelSim (SE/PE).

Do I need a mixed language or a Verilog license?

How do I run simulation with Xilinx HardIP in ModelSim without a Verilog license?


Xilinx leverages the latest encryption methodology, as specified in Verilog LRM - IEEE Std 1364-2005, to encrypt the HardIP block.

Xilinx delivers encrypted Verilog HardIP for its customers.

To support Verilog encryption technology, simulators require a Verilog license in order to run the Xilinx HardIP library of HardIP.

Note: If you already have a ModelSim Verilog License, then just run CompXlib.

The solution below is for ModelSim customers with a VHDL only license that are unable to simulate SecureIP

In order to simulate SecureIP models in ModelSim/Questa without purchasing a separate Verilog License, Xilinx and Mentor have the following solution as of the 6.4e, upcoming 6.5c, and later releases.

The solution is to provide marked secure Verilog library files available for download through this Answer Record.

This provides a facility for ModelSim VHDL only users to easily simulate SecureIP without requiring a Verilog License (i.e., Xilinx downloaded HardIP files fully support VHDL and Verilog ModelSim customers without requiring an additional Verilog license).

As of the 6.4e and later, or 6.5c and later releases (6.5 and 6.5 a/b is not supported with this patch) ModelSim PE VHDL customers can also access the new HardIP library with the new SecureIP Op software license feature. 

Refer to your local Mentor Graphics sales office for more information about how to transition from an existing SWIFT Op software to SecureIP Op software in order to enable this functionality.

ModelSim SE VHDL customers do not require a new license feature.

The files can be downloaded from the links in the internal notes:

  • For 11.2: secureip_mark_vhdl.zip
  • For 11.3: secureip_mark_vhdl_11.3.zip
  • For 11.4: secureip_mark_vhdl_11.4.zip
  • For 11.5: Customers using 11.4 do not need to install any 11.5 SecureIP updates as none of the Hard IP models were updated.

Customers using earlier versions of ISE 11 should install the 11.4 update (shown above)

The download is compatible with 6.4e, and upcoming 6.5c and later releases.

6.5a/b is not compatible with this download.

The README file contains instructions on the install.

For more information on SecureIP, refer to the Synthesis and Simulation Guide:


For additional information, refer to:

Starting in ISE 12.1 software, the Verilog files are already marked in the IDS install so no further downloads are needed.


Associated Attachments

Name File Size File Type
secureip_mark_vhdl_11.4.zip 75 MB ZIP
secureip_mark_vhdl_11.3.zip 75 MB ZIP
secureip_mark_vhdl.zip 72 MB ZIP
AR# 33118
Date 02/01/2018
Status Active
Type General Article
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • Less
Page Bookmarked