When using the ppc440mc_ddr2 memory controller with a TREFI timing parameter less than 7.8 microseconds, the required 200 microseconds initialization time is violated. TREFI might need to be set to 3.9 microseconds for some industrial DDR2 parts.
This issue can lead to intermittent DDR2 device behavior. How do I resolve this issue?
This issue is fixed in the latest ppc440mc_ddr2 core. The first version containing this fix is ppc440mc_ddr2_v2_00_b, released in EDK 11.2.