Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - UCF constraint for sys_clk incorrect for ML605

AR#	33127	Search For Another Answer
Topic	PCIe
Last Updated	08/06/2010
Status	Active

Description

Known Issue: v1.4, v1.3, v1.2, v1.1 

 

When I generate the Virtex-6 FPGA Integrated Block Wrapper for PCI Express, the created UCF is incorrect when the ML605 is selected on Page 9 of the GUI. Specifically, if I target the XC6VLX240T-FF1156-1 part and select a 100 MHz or 250 MHz Reference Clock on Page 11 of the GUI, the clock buffer and pins for sys_clk are incorrectly placed, as follows: 

 

For 100 MHz: 

 

 #NET "sys_clk_n" LOC = P6; 

 #NET "sys_clk_p" LOC = P5; 

INST "refclk_ibuf" LOC = IBUFDS_GTXE1_X0Y7; 

 

For 250 MHz: 

 #NET "sys_clk_n" LOC = V6; 

 #NET "sys_clk_p" LOC = V5; 

INST "refclk_ibuf" LOC = IBUFDS_GTXE1_X0Y4;

Solution

The IBUFDS location and pins for the 100 MHz option and the pin placement for the 250 MHz option are not correct. Users of the ML605 should change the UCF as follows: 

 

100 MHz Reference Clock: 

 #NET "sys_clk_p" LOC = P6; 

 #NET "sys_clk_n" LOC = P5; 

INST "refclk_ibuf" LOC = IBUFDS_GTXE1_X0Y6; 

 

250 MHz Reference Clock: 

 #NET "sys_clk_p" LOC = V6; 

 #NET "sys_clk_n" LOC = V5; 

INST "refclk_ibuf" LOC = IBUFDS_GTXE1_X0Y4; 

 

Revision History 

12/08/2009 - Added 250 MHz clocking information 

09/11/2009 - Updated info on pin LOCs P5 and P6 

07/13/2009 - Initial Release  

09/11/2009 - Updated info on pin LOCs P5 and P6