If an MPMC is connected to the IPLB1, and there is no peripheral / bus connected to IPLB0, an issue occurs that can lock up the PPC.
If an instruction access occurs outside of the range of the MPMC, then the access is arbitrated out to the IPLB0 processor port. However, if there is no bus or peripheral connected, there is no timeout logic to signal the processor of the condition, causing a hang. How do I resolve this issue?
A workaround is to set C_IPLB1_ADDR_BASE=0x0 and C_IPLB1_ADDR_HIGH=0xffffffff, which routes all PPC IPLB transactions to IPLB1. Accesses outside the response range of MPMC will then cause the PLB arbiter to timeout, and PPC will take the exception.