Solution

Requirements for all General ES Spartan-6 Devices

For designs that plan to use Calibrated Input Termination, the following pin locations should be used for the RZQ reference resistor:

LX Devices

XC6SLX16-2CSG324CES
==================
MCB Bank 1 - pin M13
MCB Bank 3 - pin C2

XC6SLX45-2CSG324CES
==================
MCB Bank 1 - pin M14
MCB Bank 3 - pin L6

XC6SLX45-2FGG484CES
==================
MCB Bank 1 - pin M19
MCB Bank 3 - pin K7

XC6SLX150-2FGG484CES
====================
MCB Bank 1 - pin M19
MCB Bank 3 - pin K7

XC6SLX150-2CSG484CES
====================
MCB Bank 1 - pin W20
MCB Bank 3 - pin H6

LXT Devices

XC6SLX45T-2FGG484CES
==================
MCB Bank 1 - pin P19
MCB Bank 3 - pin K7

XC6SLX150T-2FGG484CES
====================
MCB Bank 1 - pin P19
MCB Bank 3 - pin K7

XC6SLX150T-2FGG676CES
====================
MCB Bank 1 - pin U21
MCB Bank 3 - pin M10
MCB Bank 4 - pin M4
MCB Bank 5 - pin M21


Design requirements for General ES Spartan-6 device XC6SLX16-2CSG324CES when using MIG v3.1
MIG v3.2 and forward do not require these RTL changes. Please use the latest version of MIG.

Requirement 1

As specified in the device errata (document EN113):
http://www.xilinx.com/support/documentation/spartan-6.htm#131538

This General ES device does not fully support the hardware calibration operations defined in the MCB startup sequence. Note that the per-bit deskew hardware calibration of the DQ data bits initially referenced in the MCB User Guide is not be supported in any Spartan-6 devices. Therefore, to ensure a reliable memory interface:

- Follow the recommended PCB Layout Guidelines to minimize skew between DQ bits.

- For MIG 3.1, center the DQS strobe in the DQ read data capture window by editing the calibration parameters found in the top-most MIG design file (for example, <component name>.v or example_top.v) as follows:

MCB in Bank 1
C1_MC_CALIB_BYPASS = "NO"
C1_MC_CALIBRATION_MODE = "NOCALIBRATION"
C1_MC_CALIBRATION_DELAY = "HALF"

MCB in Bank 3
C3_MC_CALIB_BYPASS = "NO"
C3_MC_CALIBRATION_MODE = "NOCALIBRATION"
C3_MC_CALIBRATION_DELAY = "HALF"

- Refer to the Spartan-6 FPGA Memory Controller User Guide (UG388):
http://www.xilinx.com/support/documentation/ip_documentation/ug388.pdf

For more information on:
Calibration Parameters - see Chapter 3
PCB Layout Guidelines - see Chapter 4
MCB Startup Sequence - see Chapter 5

NOTE: These changes will be taken care of by default in the MIG 3.2 (11.3) release. Manual modification will no longer be required.

Requirement 2

For MIG 3.1, insert the following lines of Verilog code at the bottom of the "mcb_raw_wrapper.v" file, just before the "endmodule" statement.

// DQS PULLDOWN
generate
if(C_MEM_TYPE == "DDR" || C_MEM_TYPE =="MDDR" || (C_MEM_TYPE == "DDR2" && (C_MEM_DDR2_DIFF_DQS_EN == "NO"))) begin: gen_dqs_pullupdn
PULLDOWN dqs_pulldown (.O(mcbx_dram_dqs));
end else begin: gen_dqs_pullupdn_ds
PULLDOWN dqs_pulldown (.O(mcbx_dram_dqs));
PULLUP dqs_n_pullup (.O(mcbx_dram_dqs_n));
end
endgenerate

// DQSN PULLUP
generate
if((C_MEM_TYPE == "DDR" || C_MEM_TYPE =="MDDR" || (C_MEM_TYPE == "DDR2" && (C_MEM_DDR2_DIFF_DQS_EN == "NO"))) && C_NUM_DQ_PINS == 16) begin: gen_udqs_pullupdn
PULLDOWN udqs_pulldown (.O(mcbx_dram_udqs));
end else if(C_NUM_DQ_PINS == 16) begin: gen_udqs_pullupdn_ds
PULLDOWN udqs_pulldown (.O(mcbx_dram_udqs));
PULLUP udqs_n_pullup (.O(mcbx_dram_udqs_n));
end
endgenerate

NOTE: These changes will be taken care of by default in the MIG 3.2 (11.3) release. Manual modification will no longer be required.