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AR# 33139

10.1 EDK - When I use Clock Generator v2.01.a (clock_generator_v2_01_a), an error message appears during the MAP process

Description

The following error occurs during MAP when I implement an EDK-based design in Virtex-5 with the "clock_generator_v2_01_a" core:


ERROR:LIT:447 - CLKINSEL of PLL_ADV symbol 
"physical_group_ddr_clk_gen/ddr_clk_gen/PLL0_CLK_OUT<0>/ddr_clk_gen/ddr_clk_g 
en/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst" (output 
signal=ddr_clk_gen/ddr_clk_gen/PLL0_CLK_OUT<0>) is a constant 1 (choosing 
CLKIN1) but CLKIN1 is not an active signal.

How do I resolve this issue?

Solution

This issue has been fixed in the "clock_generator_v3_00_a" core and is available in EDK 11.1 at the following page:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

AR# 33139
Date Created 07/15/2009
Last Updated 11/23/2016
Status Active
Type General Article
Devices
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Less
Tools
  • EDK - 10.1
  • EDK - 10.1 sp1
  • EDK - 10.1 sp2
  • EDK - 10.1 sp3