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AR# 33149

LTE UL Channel Decoder v2.0 - When writing to and reading from the UL-CCH registers, the information is incorrect. Why?


Control data is written to the UL-CCH register(0x34), and the status data is read from the CCH Channel Status registers successfully; however, the status information read back is incorrect.


This is a known issue for LTE UL Channel Decoder data sheet DS 700. It will be fixed in the future release of the data sheet.

In the data sheet the 0x34 register UCI_OP_SIZE is defined as 5 bits. In fact, it should be 4 bits, and all the other signals should be shifted down by 1.

UL_CCH Control register

Address: 0x34

UCI_OP_SIZE : 5 bits. bits 0-3

CP :1 bit: bit 4

ACK_OP_SIZE : 2 bits ; bits 5 and 6.

USER_ID: 16 bits : bits 16 to 31

UL_CCH Status register

Address: 0x3C

STATUS_USER_ID: 16 bits: bits 0:15 This is the original USER_ID parameter of the CCH block as configured by the processor.

UCI_DATA(0..12): 13 bits : bits 16:28 Decoded UCI Data. If no UCI Data is required, then this register is set to 0. Any unused bits are set to 0.

ACK_DATA : 2 bits : bits 29:30 Decoded ACK data. Unused bits will be set to 0.

AR# 33149
Date Created 07/20/2009
Last Updated 12/15/2012
Status Active
Type General Article