PlanAhead 11.2 - DRC errors on clock placement for Spartan-3 derivatives.

AR#	33152	Search For Another Answer
Topic	SW-PlanAhead
Last Updated	07/20/2009
Status	Active

Description

Keywords: DCM, BUFG, I/O, input

When I run DRC on my Spartan-3/3E/3A/3ADSP design, I get errors on the placement of my clocking related instances. I have checked the Spartan-3 Family User Guide and my placement constraints are correct. Can I ignore these errors?

Solution

If your design meets all documented requirements, you can safely ignore these errors. This will be fixed in an upcoming PlanAhead release.