11.2 Spartan-6 PAR - Incorrect WARNING:ParHelpers:79 message
Description
I see the following message in PAR after the router is finished. When I examine the clock signal listed in FPGA Editor, I can see that they are all driven by global clock buffers and the routing is on the global routing resources. The delay and skew numbers seem reasonable too. What is this message complaining about?
WARNING:ParHelpers:79 -
The following Clock signals are not routed on the dedicated
global clock routing resources. This will usually result in
longer delays and higher skew for the clock load pins. This could
be the result of incorrect clock placement, more than 8 clocks
feeding logic in a single quadrant of the device, or incorrect
logic partitioning into the quadrant(s). Check the timing report
to verify the delay and skew for this net
Net Name: sys_clk_155_buf
Net Name: uP_clk
Net Name: sys_clk_77_buf
Net Name: sys_clk_19_buf
Solution
This warning message is sometimes incorrectly printed for Spartan-6 designs. If the delay and skew values are acceptable, the message can be safely ignored. Furthermore, the text of the message is misleading. There is no 8 clock limit or quadrant limit in Spartan-6. All 16 global clocks can be used throughout the device.
Both the false-positive issue and message content issue will be corrected in ISE version 11.4.
Applies To
Design Tools
- ISE Design Suite - 11.2
- ISE Design Suite - 11.3