AR #33163 - 11.2 System Generator for DSP - The CE_CLR pin is not available on my generated netlist when I check "Provide clock enable clear pin". Why?
11.2 System Generator for DSP - The CE_CLR pin is not available on my generated netlist when I check "Provide clock enable clear pin". Why?
| AR# | 33163 |
| Part | SW-SysGen |
| Last Modified | 2009-09-11 00:00:00.0 |
| Status | Active |
| Keywords | SysGen, sysgen, MATLAB, CE, HDL Netlist |
Description
Keywords: SysGen, sysgen, MATLAB, CE, HDL Netlist
When I generate my design to an HDL or NGC Netlist with the check box "Provide clock enable clear pin" enabled, the resulting files do not include the CE_CLR pin as they did in the past.