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11.2 System Generator for DSP - The CE_CLR pin is not available on my generated netlist when I check "Provide clock enable clear pin". Why?

AR# 33163

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Topic SW-SysGen
Last Updated 09/11/2009
Status Active
Description

Keywords: SysGen, sysgen, MATLAB, CE, HDL Netlist

When I generate my design to an HDL or NGC Netlist with the check box "Provide clock enable clear pin" enabled, the resulting files do not include the CE_CLR pin as they did in the past.

Solution

This is due to a known issue in 11.1 and 11.2. It is fixed in 11.3.
 
 
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