We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33191

11.2 BitGen - "ERROR:Bitgen:302 - Illegal value 1 for ExtMasterCclk_divide"


1 is a valid value for ExtMasterCclk_divide.

In BitGen 11.2, when I check the Enable External Master Clock option, and leave Setup External Master Clock Division as its default value of 1, the following errors occur:

ERROR:Bitgen:302 - Illegal value 1 for ExtMasterCclk_divide. It must be either 1 or an even number between 2 and 1022.

ERROR:Bitgen:157 - Bitgen will terminate because of the above errors.


This issue will be resolved in BitGen 11.3.

AR# 33191
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked