We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33194

Serial RapidIO v5.3 - Virtex-6 FPGA comma alignment set to align on even byte boundaries only


Comma alignment is set to align on even boundaries only. This is a mistake because when alignment occurs, it causes disparity errors which can eventually bring down the link.


Work around this issue by making the following changes:

In the gtx_wrapper_gtx.v or gtx_wrapper_gtx.vhd files:


on each MGT instance.

In the gtx_wrapper.xco or gtx_wrapper_vhd.xco:

CSET comma_alignment=Any_Byte_Boundary

Revision History

07/23/2009 - Initial Release

AR# 33194
Date Created 07/23/2009
Last Updated 12/15/2012
Status Active
Type General Article