The UCF provided with the Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper includes an example OFFSET constraint which enforces clock-data alignment on the receive side physical interface to within a specific data valid window.
While helpful in determining alignment, that data valid window might not meet the setup and hold requirements of the GMII or RGMII specifications. A more relaxed window is provided for some devices, primarily because of clock uncertainty resulting from the receive clock's IODELAY instance.
Proper tuning of the IDELAY taps is recommended for all designs.For details on finding the ideal settings for your design, see the LogiCORE IP Virtex-6 FPGA Embedded TEMAC User Guide (UG800).
If timing failures persist after tuning, then to reduce clock uncertainty and tighten the OFFSET constraint's data valid window, the receive clock's dedicated IODELAY should be removed.Three steps must be taken:
As a result of decreased clock delay and uncertainty, further adjustments to the IDELAY_VALUE values might be necessary to accommodate the clock-data relationship for your specific design.
For Virtex-6 lower power devices (-1L speed grade) and some Virtex-6 HXT devices, implementation of the GMII physical interface will not meet the receiver timing specification, and implementation of the RGMII physical interface receiver timing is marginal. However, proper IODELAY tuning and sufficient system margin might allow for a working system. Be sure to analyze your PHYs timing characteristics and system margin during IODELAY tuning.