Using FIFO Generator v5.2 or v5.1, if I create a Virtex-4 FPGA or Virtex-5 FPGA BRAM based FIFO, the MSBs of my output are stuck at a fixed value after a certain number of reads from the FIFO. Why?
An issue has been detected in the FIFO Generator v5.2 and v5.1, whereby the MSBs of the FIFO output can become stuck at a fixed value after a certain number of reads from the FIFO. This issue can occur if a BRAM based FIFO which uses more than one BRAM primitive also uses embedded output registers. If you encounter this issue, you can work around it by not using the embedded output registers of the BRAM.
This issue will be fixed in v5.3 of the FIFO Generator.
07/27/2009 - Initial Release