| AR# | 33241 |
| Part | SW-Chipscope Pro |
| Last Modified | 2009-08-21 00:00:00.0 |
| Status | Active |
| Keywords | logic, analyzer, ILA, ICON, VIO, LogiCORE, CSE, data, trigger |
Keywords: logic, analyzer, ILA, ICON, VIO, LogiCORE, CSE, data, trigger
When loading a new project, some signals, buses, and trigger names may be carried over. This can cause confusion when debugging and misinterpretation of results.
How can I work around this?