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AR# 33249

MIG v3.2 - Release Notes and Known Issues for ISE Design Suite 11.3

Description


This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v3.2 released in ISE Design Suite 11.3 and contains the following information:  
 
- General Information  
- Software Requirements 
- New Features  
- Resolved Issues 
- Known Issues  
 
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: 
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution


MIG v3.2 is available through ISE Design Suite 11.3.  
 
For a list of supported memory interfaces and frequencies for Spartan-3 Generation, Virtex-4 and Virtex-5 FPGA, see the MIG User Guide: 
http://www.xilinx.com/support/documentation/user_guides/ug086.pdf
 
For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA MCB, see the Spartan-6 FPGA Memory Controller User Guide: 
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
 
For a list of supported Spartan-6 FPGAs, see (Xilinx Answer 33234)
 
For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the Virtex-6 FPGA Memory Interface Solutions User Guide: 
http://www.xilinx.com/support/documentation/user_guides/ug406.pdf
 
 
Software Requirements 
- Xilinx ISE Design Suite 11.3 
- Synplify Pro C-2009.06 support (Synplify support available for Virtex-5, Virtex-4, and Spartan-3 Generation only) 
- 32-bit Windows XP 
- 32-bit Linux Red Hat Enterprise 4.0 
- 64-bit/32-bit Linux Red Hat Enterprise 4.0 
- 64-bit XP professional 
- 32-bit Vista business 
- 64-bit SUSE 10 
- 64-bit/32-bit Linux Red Hat Enterprise 5.0 support 
- 64-bit Windows Vista support 
- 32-bit SUSE 10 support 
 
 
New Features 
- ISE Design Suite 11.3 software support 
- Virtex-6 FPGA RLDRAM II support 
- Virtex-6 FPGA HXT support for all designs 
- Virtex-6 FPGA Low Power and CXT parts support for DDR2/DDR3 SDRAM designs 
- Virtex-6 FPGA DDR3 SDRAM and QDRII+ SRAM Multiple Controller support 
- Outer banks support for Virtex-6 FPGA DDR2 and DDR3 SDRAM designs 
- Up to 144-bit data widths support for Virtex-6 FPGA DDR2 and DDR3 SDRAM designs 
- ECC support for Virtex-6 FPGA DDR2 and DDR3 SDRAM designs 
- Debug port support for all Virtex-6 FPGA designs 
- Support for Synplicity version C-2009.06 
- Spartan-6 FPGA VHDL support 
 
 
Resolved Issues 

DDR2/DDR3 SDRAM Virtex-6 FPGA 
 
- (Xilinx Answer 32930) MIG v3.1, Virtex-6 FPGA DDR3 - Changes required to simulation testbench (sim_tb_top.v) to skip calibration and avoid memory overflow errors 
- (Xilinx Answer 32830) MIG v3.1, Virtex-6 FPGA DDR2 - Master Bank must be selected in GUI even when default banks are used 
- (Xilinx Answer 32873) MIG v3.1, Virtex-6 FPGA DDR2/DDR3 - False memory model violations might occur in simulation 
- When Virtex-6 FPGA design simulations are run using ModelSim, it will report an error "NAN". The details of the error message and the cause of the error is added to ug406. 
-- (Xilinx Answer 32872) MIG v3.1, Virtex-6 FPGA - # ** Error: (vsim-8604) NaN results from division operation 
- For Virtex-6 DDR2/DDR3 SDRAM designs, end address value is limited to 10 bits in sim_tb_top.v module in sim folder of the MIG output 
-- CR 524624 
- Virtex-6 FPGA DDR2/DDR3 SDRAM: Provided separate PERIOD constraint for BUFR clocks in UCF 
-- CR 526447 
- Corrected the MMCM parameters CLKFBOUT_MULT_F and CLKOUT_DIVIDE for Virtex-6 DDR2, DDR3 SDRAMs and QDRII+ SRAM designs 
-- CR 526038 
- Initialized the RTT_NOM and RTT_WR parameters in the top level for DDR3 SDRAM designs 
-- CR 524700 
 
QDRII+ SRAM Virtex-6 FPGA  

- (Xilinx Answer 32925) MIG v3.1, Virtex-6 FPGA QDRII+ - Issues exist in calibration logic that require an updated phy_read_stage1_cal.v module 
- (Xilinx Answer 32870) MIG v3.1, Virtex-6 FPGA QDRII+ SRAM - MIG does not properly restrict Data Read group bank selection which could result in ERROR: Place:906 during MAP 
- When Virtex-6 FPGA design simulations are run using ModelSim, it will report an error "NAN". The details of the error message and the cause of the error is added to ug406. 
-- (Xilinx Answer 32872) MIG v3.1, Virtex-6 FPGA - # ** Error: (vsim-8604) NaN results from division operation 
-- CR 523075 
- Corrected the MMCM parameters CLKFBOUT_MULT_F and CLKOUT_DIVIDE for Virtex-6 DDR2, DDR3 SDRAMs and QDRII+ SRAM designs 
-- CR 526038 
 
Spartan-6 FPGA MCB 

- (Xilinx Answer 32924) MIG v3.1, Spartan-6 FPGA MCB - When controllers C1, C2, and C4 are selected, C4 can only be selected as DDR2 SDRAM. 
- (Xilinx Answer 32869) MIG v3.1, Spartan-6 FPGA MCB - When a MIG MCB project is reloaded using Recustomize (Under Original Settings) display issues occur 
- Fixed syntax error in veo output file for Spartan-6 FPGA design 
-- CR 523477 
 
DDR2 SDRAM Virtex-5 FPGA 

- (Xilinx Answer 32610) MIG 3.1, Virtex-5 FPGA DDR2 - TWTR violations might occur at low frequencies in simulation and hardware  
- (Xilinx Answer 32871) MIG v3.1, Virtex-5 FPGA DDR2 SDRAM - TWR violations occur at low frequencies 
- (Xilinx Answer 32919) MIG v3.1, Virtex-5 FPGA - Verilog designs using Synplify Pro C-2009.03 will fail in MAP with "ERROR:MapLib:1114" 
- Modified the MAXDELAY constraint path on en_dqs signal by using a wild character to enable the tools to properly analyze the MAXDELAY  
-- CR 525635 
- MAXDELAY violations in DDR designs are resolved with Predictable IP constraints of ISE  
-- CR 517594 
- Multiple interface single ended clock designs, IBUFG gets instantiated in one of the infrastructure modules  
-- CR 510214 
 
DDR SDRAM Virtex-5 FPGA 

- (Xilinx Answer 32919) MIG v3.1, Virtex-5 FPGA - Verilog designs using Synplify Pro C-2009.03 will fail in MAP with "ERROR:MapLib:1114" 
 
QDRII SRAM Virtex-5 FPGA
 
- (Xilinx Answer 32375) MIG 2.3/3.0, Virtex-5 FPGA QDRII - Potential for small margin between the CQ and FPGA clock after stage 2 calibration for frequencies between 125 - 250 MHz 
- (Xilinx Answer 32919) MIG v3.1, Virtex-5 FPGA - Verilog designs using Synplify Pro C-2009.03 will fail in MAP with "ERROR:MapLib:1114" 
- Fixed an issue of CQ/Q centering off at low frequencies 
-- CR 525895 
 
DDRII SRAM Virtex-5 FPGA  

- (Xilinx Answer 32919) MIG v3.1, Virtex-5 FPGA - Verilog designs using Synplify Pro C-2009.03 will fail in MAP with "ERROR:MapLib:1114" 
 
DDR2 SDRAM Virtex-4 FPGA Direct Clocking 
 
DDR2 SDRAM Virtex-4 FPGA Serdes Clocking  
 
DDR SDRAM Virtex-4 FPGA 
 
QDRII SRAM Virtex-4 FPGA 
 
DDRII SRAM Virtex-4 FPGA 
 
DDR/DDR2 SDRAM Spartan-3 FPGA 
 
Updates to Virtex-5, Virtex-4, and Spartan-3 Generation FPGA MIG User Guide (ug086) 
- Corrected the incorrect signal direction for DCI/SSTL18_I selection under Memory Implementation Guidelines, I/O standards section. 
-- CR 524304 
- Provided information on using full memory array for DDR2/DDR3 SDRAM simulations 
-- CR 519171 
- Added notes on how to achieve better timing for MIG generated designs 
-- CR 506948 
 
MIG Tool  

- Combined the "Verify UCF" and "Update Design" features into "Verify UCF and Update Design and UCF" 
-- CR 506635 
- MIG supports more input UCF formats for Verify UCF and Update Design flows 
-- CR 506633 
- Enhanced the description of the Pin Compatibility page 
-- CR 505273 
- Provides detailed Verify UCF error messages when a signal group in the input UCF file is moved to a different bank that is not selected in the input mig.prj file 
-- CR 526296 
- Added support for 1GB DDR2 SDRAM MT8HTF12864HY-667 SODIMM for Virtex-4, Virtex-5 and Spartan FPGA families 
-- CR 525667 
- Removed the '-s' speed option from TRCE command in ise_flow.bat file. It is not required to specify this option in TRCE command 
-- CR 525629 
- MIG outputs the correct migcore_readme.txt for Spartan6 FPGA 
-- CR 525409 
- To create a custom memory part it is not required to have read/write permissions in the XILINX install area, this notes is removed from the description of Create Custom Part window 
-- CR 525329 
- The Bank Selection page only lists banks with at least one DCI input signals as Master Bank options 
-- CR 523715 
- Removed the additive latency support for Virtex-6 FPGA DDR2 SDRAM from MIG GUI 
-- (Xilinx Answer 32839) MIG v3.1, Virtex-6 FPGA DDR2/DDR3 SDRAM - Non-zero values for Additive Latency are not supported 
-- CR 523338 
- Copyright and legal header information is updated for all Virtex-6 FPGA designs as per the latest header format 
-- CR 523279 
- Provided the full part name for DDR3 SDRAM RDIMM memory part MT9JSF12872XX-1G1 as this name matches with UDIMM name 
-- (Xilinx Answer 32874) MIG v3.1, Virtex-6 FPGA DDR3 SDRAM- MIG lists support for the MT9JSF12872XX-1G1, which could represent two different Micron devices 
-- CR 523273 
- Resolved the delay in controller options page switching when the selection is changed from Virtex-6 FPGA DDR3 SDRAM to Virtex-6 FPGA QDRII+ SRAM 
-- CR 523095 
- MIG generates 40,48 data width designs for Virtex-6 FPGA DDR2 SDRAM, x16 2Gb parts with default bank selections 
-- CR 523076 
- MIG outputs correct pin count for System Control group in datasheet.txt for User Design 
-- CR 522372 
- MIG provides two selection buttons "Accept" and "Decline" for Simulation Memory Model License Agreement 
-- CR 522363 
- MIG allows user to select only legal values of RTT for Virtex-6 FPGA DDR3 SDRAM 
-- CR 522311 
- For ECC enabled Virtex-6 FPGA DDR3 SDRAM designs, DM pins will not be assigned 
-- CR 521722 
- Corrected the full_mem_bits parameter value in DDR memory model parameter file 
-- CR 519171 
- MIG GUI will show all the memory parts irrespective of the frequency selected with a warning symbol for the parts that do not support the selected frequency 
-- CR 518815 
- MIG allocates DQ pins within the clock regions of its associated DQS signal for Virtex-4 FPGA DDR2 SDRAM SerDes designs 
-- CR 513309 
- Resolved the MIG batch mode DISPLAY issue. User is able to generate the MIG design in Batch mode when no DISPLAY is set for the environment 
-- CR 505163 
 
 
Known Issues  
- ISE Design Suite 11.3 does not support bitstream generation for VIrtex-6 FPGA HXT devices. MIG allows core generation targeting HXT devices however, the output designs will only pass implementation (i.e., Translate, MAP, PAR). Bitstream generation support is scheduled to be added in ISE Design Suite 11.4. 
 
Virtex-6 FPGA DDR2/DDR3 SDRAM 
(Xilinx Answer 33389) MIG v3.2, Virtex-6 FPGA DDR3 - ODT values incorrectly set for component-based design 
(Xilinx Answer 33288) MIG v3.2, Virtex-6 FPGA DDR2/3: Calibration does not complete or completes incorrectly for x4 memory parts  
(Xilinx Answer 33403) MIG v3.2, Virtex-6 FPGA DDR2/DDR3: Simulation warnings are generated for mismatches in port connection sizes 
(Xilinx Answer 33405) MIG v3.2 Virtex-6 FPGA DDR2/DDR3: When data mask is disabled, BitGen will fail with PhysDesignRules errors 
(Xilinx Answer 33249) MIG v3.2, Virtex-6 FPGA DDR3: Designs targeting x8 devices with a 72-bit data width will fail with ERROR:Place:899 if Address/Control and System Control are in the same FPGA bank  
(Xilinx Answer 33409) MIG v3.2, Virtex-6 FPGA DDR2 and DDR3 - Traffic Generator (example_design) does not support DDR2 BL=4 and DDR2/DDR3 Data Widths greater then 72-bits  
(Xilinx Answer 33415) MIG v3.2, Virtex-6 FPGA DDR2DDR3 - Master Bank selection is not enabled in some cases which require a Master Bank  
(Xilinx Answer 33418) MIG v3.2, Virtex-6 FPGA DDR3 - When targeting a RDIMM with CWL=7, the design does not drive the correct write data in OTF mode 
(Xilinx Answer 33419) MIG v3.2, Virtex-6 FPGA DDR3: No support available for CWL=8 for RDIMM devices  
(Xilinx Answer 33420) MIG v3.2, Virtex-6 FPGA DDR2 - No support for CL=6 with RDIMM devices 
(Xilinx Answer 33439) MIG v3.2, Virtex-6 FPGA DDR2/DDR3 - ECC not supported for data widths equal to 120-bit 
(Xilinx Answer 33440) MIG v3.2, Virtex-6 FPGA DDR2 - When ODT is disabled (RTT_NOM = 0), ODT is incorrectly asserted immediately following calibration 
(Xilinx Answer 33441) MIG v3.2, Virtex-6 FPGA DDR2/DDR3 - The periodic reads associated with the phase detector are not properly sent according to the tPRDI timing parameter 
(Xilinx Answer 33249) MIG v3.2, Virtex-6 FPGA DDR3: tRP violations may occur in simulation due to rounding error 
(Xilinx Answer 33443) MIG v3.2, Virtex-6 FPGA DDR2/DDR3 - Read associated with Read Modified Write command is incorrectly issued as a Read with Auto-Precharge 
(Xilinx Answer 33613) MIG v3.2, Virtex-6 DDR2/DDR3: Design incorrectly assigns app_wdf_mask (user interface data mask) to 0 preventing the ability to mask data. 
 
Virtex-6 FPGA QDRII+ SRAM<\u> 

(Xilinx Answer 33289) MIG v3.1, v3.2, Virtex-6 FPGA QDRII+ - Changes required to Samsung simulation model for proper operation and completion of calibration 
(Xilinx Answer 33378) MIG v3.2, VIrtex-6 FPGA QDRII+/RLDRAMII: Half-cycle path from ISERDES to clk_RD is not required 
(Xilinx Answer 33413) MIG v3.2, Virtex-6 FPGA QDRII+ SRAM - The output example_top.ucf is missing the system clock period constraint and includes an incorrect BUFR constraint 
 
Virtex-6 RLDRAMII 
(Xilinx Answer 33375) MIG v3.2, Virtex-6 FPGA RLDRAMII - Valid configurations to avoid tRC violations for -18, -25, -25E, and -33 devices 
(Xilinx Answer 33249) MIG v3.2, Virtex-6 FPGA RLDRAMII: MAX tCK violations occur in simulation for -18 parts running at 370 MHz 
(Xilinx Answer 33377) MIG v3.2, Virtex-6 FPGA RLDRAMII - Design is unroutable when Debug Signals are turned on 
(Xilinx Answer 33378) MIG v3.2, VIrtex-6 FPGA QDRII+/RLDRAMII: Half-cycle path from ISERDES to clk_RD is not required 
(Xilinx Answer 33402) MIG v3.2, Virtex-6 FPGA RLDRAMII - Data Mask signals are not properly propagated through the write path - RTL CHANGES REQUIRED 
(Xilinx Answer 33446) MIG v3.2, Virtex-6 FPGA RLDRAMII - ERROR:Bitgen - Could not find programming information occurs for the XC6VLX760-FF1760 device 
 
Spartan-6 FPGA MCB  
(Xilinx Answer 33356) Spartan-6 FPGA MCB - X4 memory components are not supported until IDS 11.4 (MIG 3.3)  
(Xilinx Answer 33357) Spartan-6 FPGA MCB - Port 3 is not supported in read mode when all 6 ports are configured 
(Xilinx Answer 33358) Spartan-6 FPGA MCB: ERROR:Place:864 errors occur during PAR when data mask is disabled  
(Xilinx Answer 33417) Spartan-6 FPGA MCB - Spartan-6 FPGA Memory Controller User Guide (UG388) incorrectly states that MIG automatically outputs files for the SP601/SP605 reference boards 
 
Virtex-4 and Virtex-5 FPGA DDR/DDR2 SDRAM  
(Xilinx Answer 33414) MIG v3.2, Virtex-4/Virtex-5 FPGA DDR/DDR2 - MIG GUI incorrectly enables Data Mask check box for X4 RDIMM parts which do not have a DM 
 
MIG Tool  
(Xilinx Answer 32320) MIG 3.0 - Issues can occur when generating/regenerating a MIG project with the same component name
AR# 33249
Date Created 09/09/2009
Last Updated 10/14/2014
Status Active
Type General Article
Tools
  • ISE Design Suite - 11.3
IP
  • MIG