LogiCORE IP DisplayPort - Release Notes and Known Issues

Description

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator software and LogiCORE IP Display Port Core. 

The following information is listed for each version of the core: 

• New Features 
• Bug Fixes 
• Known Issues 

Solution

• (Xilinx Answer 42953) Design Advisory for LogiCORE IP DisplayPort Master Answer Record
• (Xilinx Answer 34210) How do I connect the Display Port Core to my DisplayPort connector?

• Initial Release in ISE Design Suite 13.2

• Virtex-7
• Kintex-7
• Virtex-6 XC LXT/SXT/HXT
• Spartan-6 XC LXT
• Spartan-6 XA LXT

• ISE Design Suite 13.2 software support

• CR 610594 - Tx framing logic does not send last byte of line data on to main link.
• CR 608226 - i_last_pixel , i_line_done & i_sterring_count registers have CDC issue.
• CR 605875 - Issue in I2C Write burst to additional I2C slave.
• CR 593604 - Fully packed TU logic fixed.
• CR 593470 - Sink response with valid data for address only write command with MOT set to '1'
• CR 592998 - Interrupt clear on read to interrupt status register logic fixed.
• CR 591942 - no-video assertion looks at wrong bit selection of vbid.
• CR 587716 - Sink core:AUX Write Status_Request transaction needs to be handled.
• CR 587715 - Sink core: SYMBOL_ERROR_COUNT register implementation is incorrect.
• CR 582256 - Source: User/framing logic misbehaves with 1680 pixel frame @ 10bpc, 4 lanes @ 2.7G.
• CR 573034 - Sink core: DPCD structure made accessible from APB/AXI for advanced users.

• (Xilinx Answer 42952) Virtex-5 device support has been removed.
• (Xilinx Answer 42810) Why does the reference design have timing violations? 
• (Xilinx Answer 43176) Why is the CORE_ID register different for the Source and Sink cores?
• (Xilinx Answer 44843) Does the DisplayPort I2C over AUX support clock stretching for slower I2C slave?
• (Xilinx Answer 45278) Why do I get an error in MAP for the Hot Plug Detect (HPD) pin, when trying to target Kintex-7? 

• Initial Release in ISE Design Suite 13.1

• Virtex-6 XC LXT/SXT/HXT
• Spartan-6 XC LXT
• Spartan-6 XA LXT
• Virtex-5 XC LXT/SXT/TXT/FXT

• ISE Design Suite 13.1 software support

• CR 561918 - S6 & V6 unified wrapper files are needed.
• CR 580813 - Response with min number of sync pulses is ignored by source.
• CR 581723 - With some configurations source transmits zero length TUs that affects display.
• CR 582925 - V5 with legacy interface (APB) is needed.
• CR 587682 - Handshake mismatching between I2C sink and AUX response causes continuous I2C defers.
• CR 587685 - The M value generated in dual-pixel mode is 1/2 the expected value.
• CR 587714 - Video interrupt is generated immediately after no-video. Delayed the assertion for proper MSA availability.
• CR 587715 - Symbol error counter for lane 2 and lane 3 has init issue.
• CR 587722 - PRBS7 connectivity is not proper in Virtex-6 PHY.

• (Xilinx Answer 35037) How do I use the 2 vid_enable output pins on the Display Port Sink core?
• (Xilinx Answer 35075) What are the MAX_LINK_RATE, MAX_LANE_COUNT and other values defined by the VESA Display Port v1.1a specification?
• (Xilinx Answer 44843) Does the DisplayPort I2C over AUX support clock stretching for slower I2C slave? 

• Initial Release in ISE Design Suite 12.3

• Virtex-5 LXT
• Virtex-5 SXT
• Virtex-5 TXT
• Virtex-5 FXT
• Spartan-6 LXT
• Virtex-6 LXT
• Virtex-6 SXT
• Virtex-6 HXT

• ISE Design Suite 12.3 software support

• CR 570896 - GTP_DUAL_X0Y0 needs GTP_DUAL_X0Y1 instantiated. As per recommendation constraints are updated.
• CR 568660 - Writes to DPCD address 0x0600 return NACK.
• CR 565479 - Pixel loss is seen when using 10/8 BPC in YCbCr422 format.
• CR 559333 - A rare case occurring where data is getting unaligned after training is done.

• (Xilinx Answer 35037) How do I use the 2 vid_enable output pins on the Display Port Sink core?
• (Xilinx Answer 35075) What are the MAX_LINK_RATE, MAX_LANE_COUNT and other values defined by the VESA DisplayPort v1.1a specification?
• (Xilinx Answer 44843) Does the DisplayPort I2C over AUX support clock stretching for slower I2C slave? 

• Initial Release in ISE Design Suite 12.2

• ISE 12.2 software support
• Virtex-6 support

• CR # 557442 - When connecting the Rx and Tx example designs together, it causes contention on the AUX bus. This has been resolved in 12.2.
• CR # 557203 - The toplevel file contains the ports for both Tx and Rx links, resulting in port mismatch errors when Tx or Rx core is generated. This has been resolved in 12.2.
• CR #: 557137 - The lane count in defines.v file is hardcoded to a value of 4. This has been changed to take the value configured during core generation.
• CR #: 557134 - Different file names have been created for Tx and Rx example designs in 12.2.
• (Xilinx Answer 34829) Why do I receive an error about the GTP_DUAL, when I target a Virtex-5 TXT device?
  CR #: 554267 - The ejava files for the Tx, Rx and TxRx have been updated to use a GTX wrapper when the selected device is V5 FXT or V5 TXT.
• CR #: 559502 - The device name in the xst_scr.ejava file is hardcoded to a specific value. This has been updated to match the device. selected by the user during core generation.
• CR #: 538464 - The .vho file for the source core was not formatted correctly, resulting in a syntax error during synthesis.
• (Xilinx Answer 33888) LogiCORE IP Display Port v1.1 - The example design does not meet timing when I target a Spartan-6 device. Why?
• (Xilinx Answer 35403) Why does the core fail to train when the MIN_PRE_EMPHASIS register is set to any value other than zero.

• (Xilinx Answer 35037) How do I use the 2 vid_enable output pins on the Display Port Sink core?
• (Xilinx Answer 35075) What are the MAX_LINK_RATE, MAX_LANE_COUNT and other values defined by the VESA Display Port v1.1a specification?
• (Xilinx Answer 44843) Does the DisplayPort I2C over AUX support clock stretching for slower I2C slave? 

• Initial Release in ISE Design Suite 12.1

• ISE 12.1 software support
• Addition of Secondary Channel Audio support
• Virtex-6 support

• (Xilinx Answer 33890) LogiCORE IP Display Port v1.1 - Why does my Display Port Receiver Sink core not work correctly when I have a single active lane and the user interface is forced to 2 bits wide?
  CR #: 539132 - For the Sink core, when the user would set the user pixel width to 2 (0x010) and force the user pixel width to 2 (0x008) when the number of active lanes is only 1, the data would arrive to the user incorrectly.
• (Xilinx Answer 33885) LogiCORE IP Display Port v1.1 - Why does my VHDL Instantiation template fail when I attempt to simulate or synthesize the transmitter source design?
• (Xilinx Answer 33886) LogiCORE IP Display Port v1.1 - DCM Wrapper needs to be changed to use high-frequency mode for the Display Port Receiver Sink Example design to work properly under all circumstances.
• (Xilinx Answer 33887) LogiCORE IP Display Port v1.1 - Why is my HSYNC timing incorrect when using the dual pixel mode for some frequencies?
• (Xilinx Answer 34671) Why do I see a simulation error with the Display port example design 11.5?

• (Xilinx Answer 33889) Where can I find the Getting Started Guide for the Display Port Core?
• (Xilinx Answer 33888) LogiCORE IP Display Port v1.1 - The example design does not meet timing when I target a Spartan-6 device. Why?
• (Xilinx Answer 34829) Why do I receive an error about the GTP_DUAL, when I target a Virtex-5 TXT device?
• (Xilinx Answer 35037) How do I use the 2 vid_enable output pins on the Display Port Sink core?
• (Xilinx Answer 35075) What are the MAX_LINK_RATE, MAX_LANE_COUNT and other values defined by the VESA Display Port v1.1a specification?
• (Xilinx Answer 35403) Why does the core fail to train when the MIN_PRE_EMPHASIS register is set to any value other than zero?
• (Xilinx Answer 44843) Does the DisplayPort I2C over AUX support clock stretching for slower I2C slave? 

• Initial Release in ISE Design Suite 11.4

• ISE Design Suite software support 11.4
• Initial Release

• N/A

• (Xilinx Answer 33885) does my VHDL Instantiation template fail when I try to simulate or synthesize my transmitter source design?
• (Xilinx Answer 33886) Wrapper needs to be changed to use high-frequency mode for the Display Port Receiver Sink Example design to work properly under all circumstances.
• (Xilinx Answer 33887) is my HSYNC timing incorrect when using the dual pixel mode for some frequencies?
• (Xilinx Answer 33888) does the example design not meet timing when targeting a Spartan-6 device?
• (Xilinx Answer 33889) can I find the Getting Started Guide for the Display Port core?
• (Xilinx Answer 33890) does my Display Port Receiver Sink core not work correctly when I have a single active lane and the user interface is forced to 2-bits wide?
• (Xilinx Answer 34671) do I see a simulation with the Display port example design 11.5?
• (Xilinx Answer 34829) do I receive an error about the GTP_DUAL, when I target a Virtex-5 TXT device?
• (Xilinx Answer 35037) do I use the 2 vid_enable output pins on the Display Port Sink core?
• (Xilinx Answer 35075) What are the MAX_LINK_RATE, MAX_LANE_COUNT and other values defined by the VESA Display Port v1.1a specification?
• (Xilinx Answer 44843) Does the DisplayPort I2C over AUX support clock stretching for slower I2C slave?