Xilinx leverages the latest encryption methodology as specified in Verilog LRM - IEEE Std 1364-2005.
Simulation models for the Hard-IP such as the PowerPC processor, MGT, and PCIe leverage this technology.
For more information, see the Synthesis and Simulation guide at:
There are special requirements for licensing which are also listed in the Synthesis and Simulation Guide.
Starting in 11.1, SecureIP flow is supported by all Xilinx simulation vendor partners.
SecureIP Frequently Asked Questions (FAQs):
Q1) Does ISim support HARD IP blocks?
A1) HARD IP Blocks are fully supported in ISim without additional setup.
Q2) Does MXE support HARD IP blocks or SecureIP?
Q3) Does Aldec support HARD IP blocks or SecureIP?
A3) Yes. See (Xilinx Answer 32100).
Q4) How do I simulate SecureIP with ModelSim and Questa?
A4) See (Xilinx Answer 32936).
Q5) How do I run simulation with Xilinx SecureIP in ModelSim without a Verilog license?
A5) See (Xilinx Answer 33118).
Q6) Does NCSIM and VCS support SecureIP flow in ISE 10.1?
A6) "See (Xilinx Answer 30975).
Q7) How do I simulate SecureIP with VCS?
A7) See (Xilinx Answer 32937).
Q8) How do I compile SecureIP libraries with VCS 2008.12?
A8) See (Xilinx Answer 32820).
Q9) How do I simulate SecureIP with NCSim?
A9) See (Xilinx Answer 31060).