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AR# 33276

Virtex-6 FPGA Integrated Block Wrapper v1.3, v1.3 rev 2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1

Description

This Release Notes and Known Issues Answer Record is for the Virtex-6 FPGA Integrated Block Wrapper v1.3 rev 2 for PCI Express, released in ISE Design Suite 11.3 and ISE 12.1, and contains the following information:
  • General Information
  • New Features
  • Bug Fixes
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

General Information

The issue described in (Xilinx Answer 35681) is fixed in v1.3 rev 2 and later 1.3 versions for ES silicon.

The Virtex-6 FPGA Integrated Block Wrapper for PCI Express is shipped with a free license. See (Xilinx Answer 33386) for more information.

There is a v1.3 rev 2 patch available for installation with ISE 12.1. See (Xilinx Answer 34279) to get this patch. All ES silicon users should update to ISE 12.1 or later with v1.3 rev 2.

NOTE: The Virtex-6 FPGA Integrated Block Wrapper v1.3 rev 2 for PCI Express only supports General ES silicon. Please refer to the errata document provided with your devices to determine which silicon you have. For "Initial ES" silicon, you must use the v1.2 core.

New Features
  • ISE 11.3 software support
  • Virtex-6 FPGA Integrated Block for PCI Express Root Port support
  • Implementation support for 512 Bytes MPS configuration for the 8-lane Gen2 product.
  • Implementation support for all part/packages for the 8-lane Gen2 product
  • Added support for 6VHX380T-FF1155-1.
Resolved Issues
CR 517195: Error in generating core from ISE New source Wizard
Issue resolved where ProjNav would error out with a Tcl scripting error when attempting to generate the core from ISE New Source Wizard.

CR 523072: Incorrect UCF path in implement.bat file
Issue resolved where the relative path to UCF in implement.bat is incorrect, when design is generated and implemented on Windows operating systems.

CR 511334: BUFG driving MMCM clkin removed
The BUFG driving the MMCM clkin was removed, to reduce the number of BUFGs used in the design.

CR 509679: Root Port operation now supported in this release.
Support added for Root Port operation of the PCIe Integrated Block.

CR 524324: FIFO_LIMIT setting could cause throttling on Transaction Transmit interface for the 8-lane Gen2 operation only
Issue resolved where the FIFO_LIMIT setting in the 8-lane Gen2 product was not high enough and could cause throttling on the Transaction transmit interface.

CR 524835: Incorrect cfg_trn_pending_n functionality
Issue resolved where the cfg_trn_pending_n output of the core was inverted.

CR 522979: Implementation support for the 8-lane Gen2 product with 512 Bytes Max Payload Size Configuration
Implementation support is now available for the 8-lane Gen 2 product with 512 Bytes Max Payload Size Configuration

CR 522735: Support for Non-default User Interface frequency when the Xilinx Development Board selected is "ML 605"
Implementation support is now available for non-default User Interface frequency when the Xilinx Development Board selected is "ML 605".

CR 522902: Support for Programmed Power Management (PPM) state L1 for the 8-lane Gen2 product
Programmed Power Management (PPM) state L1 is now supported for the 8-lane Gen2 product

CR 522593: trn_reof_n assertion without a trn_rsof_n assertion on Receive Transaction Interface in the 8-lane Gen2 product, when receiving back-to-back Transactions.
Issue resolved where trn_reof_n might assert without trn_rsof_n assertion if trn_rsrc_rdy_n were deasserted while a packet was being written into the internal FIFO.

CR 525136: Requirement added for trn_tsrc_dsc_n assertion to be accompanied by trn_teof_n assertion in the 8-lane Gen2 product
The 8-lane Gen2 product now requires trn_tsrc_dsc_n assertion to be accompanied by trn_teof_n assertion.

CR 525691: Transmit Transaction interface lock-up in the 8-lane Gen2 product.
Issue resolved where the Transmit Transaction interface locks up on an assertion of trn_teof_n, which is not qualified by trn_tsrc_rdy_n, in the 8-lane Gen2 product.

Known Issues
Virtex-6 FPGA solutions are pending hardware validation.

(Xilinx Answer 32915) - Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - Use of trn_rnp_ok_n not supported for the 8-lane Gen 2 Integrated Block Mode
(Xilinx Answer 32932) - Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - VHDL Example Design and Testbench not available
(Xilinx Answer 32934) - Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - 250 MHz Reference Clock Required for GEN 2 Mode of Operation
(Xilinx Answer 33106) - Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - ModelSim simulation does not show all signals in hierarchy
(Xilinx Answer 34739) - Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - Incorrect MMCM VCO settings result in "ERROR:PhysDesignRules:1995 - The computed value for the VCO operating frequency..."
(Xilinx Answer 34980) - Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - No power management support in x8 Gen 2 mode
(Xilinx Answer 35426) - Virtex-6 FPGA Integrated Block for PCI Express - The v1.3, v1.3 rev 1,v1.4, and v1.4 rev 2wrapper might not link train on startup when using ISE Design Suite 11.5 or later
(Xilinx Answer 36008) - Virtex-6 FPGA Integrated Block Wrapper for PCI Express - The v1.3 and v1.3 rev 1 Core is Not Linking Up Reliably on ES (engineering sample) silicon Using ISE 12.1 and ISE 11.5 or later software
(Xilinx Answer 36677) - Virtex-6 FPGA Integrated Block Wrapper v1.3 rev 2 and v1.5 for PCI Express - Updated MGT Settings

Revision History
08/09/2010 - Added information about 35681.
07/19/2010 - Updated Note regarding ES Silicon
07/08/2010 - Added 36677
06/08/2008 - Added 36008
05/03/2010 - Added 35426
03/30/2010 - Added 34980
03/16/2010 - Added 34739
09/25/2009 - Added ES silicon support info to General Information
09/16/2009 - Initial Release

Linked Answer Records

Child Answer Records

Associated Answer Records

AR# 33276
Date Created 09/09/2009
Last Updated 05/22/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 LXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )