AR #33277 - Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.3
Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.3
| AR# | 33277 |
| Part | IP-SysIO-PCI Express Block |
| Last Modified | 2009-11-10 00:00:00.0 |
| Status | Active |
| Keywords | PCIe, wrapper |
Description
Keywords: PCIe, wrapper
This Release Notes and Known Issues Answer Record is for the Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express, released in ISE Design Suite 11.3, and it contains the following information:
- General Information
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator interface known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf
Solution
General InformationThe Virtex-6 FPGA Integrated Block Wrapper for PCI Express is shipped with a free license. See (Xilinx Answer 33386) for more information.
New Features
- ISE Design Suite 11.3 support
- VHDL source for wrapper and example design
- Support for VCS, IUS, and Synplify
- Additional Part/Package support
Resolved Issues
CR 520833: Clock-to-out delay required on cfg_interrupt_n for simulation
(Xilinx Answer 32865)
CR #522729: Designs which use Multi-Vector MSI should check the number of allocated vectors before generating an MSI interrupt; this does not apply to endpoints and was removed from the v1.1 release notes. It is listed in this solution so users know why it was removed.
CR #522731: Designs which use the cfg_pm_wake_n input to generate a PME event should implement a timeout counter.
(Xilinx Answer 32867)
Known Issues
Spartan-6 FPGA solutions are pending hardware validation.
(Xilinx Answer 33761) - Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - How to Enable use of a 100 MHz Reference Clock
(Xilinx Answer 33774) - Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - 250 MHz Is Not a Valid Reference Clock Option
Revision History
11/09/2009 - Added AR 33774.
11/05/2009 - Added AR 33761
09/16/2009 - Initial Release