General Information

Important Note about Versions and Patches

ISE 11.5 contains an updated version of the ISE 11.4 v1.2 wrapper files. When generated these wrapper files are versioned as v1.2 rev 1, and this is noted in the readme that is generated with the wrapper files. See the generated readme for infomration on new features and changes in this version.

The Spartan-6 FPGA Integrated Block Wrapper for PCI Express is shipped with a free license. See (Xilinx Answer 33386) for more information.

New Features

• ISE Design Suite 11.3 support
• VHDL source for wrapper and example design
• Support for VCS, IUS, and Synplify
• Additional Part/Package support

Resolved Issues
CR 520833: Clock-to-out delay required on cfg_interrupt_n for simulation
(Xilinx Answer 32865)

CR #522729: Designs which use Multi-Vector MSI should check the number of allocated vectors before generating an MSI interrupt; this does not apply to endpoints and was removed from the v1.1 release notes. It is listed in this solution so users know why it was removed.

CR #522731: Designs which use the cfg_pm_wake_n input to generate a PME event should implement a timeout counter.
(Xilinx Answer 32867)

Known Issues
Spartan-6 FPGA solutions are pending hardware validation.

(Xilinx Answer 33761) - Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - How to Enable use of a 100 MHz Reference Clock

(Xilinx Answer 33774) - Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - 250 MHz Is Not a Valid Reference Clock Option

(Xilinx Answer 33918) - Virtex-6, Spartan-6 FPGA and Block Plus Integrated Block Wrappers for PCI Express- Why is the root port model and testbench provided with the example simulation not passing Memory or I/O transactions to the user side interface?

(Xilinx Answer 34101) - Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - cfg_err_cpl_unexpect_n port is not available

(Xilinx Answer 34166) - Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - VHDL Testbench Files

v1.2 rev 1 Known Issues

(Xilinx Answer 34341) - Spartan-6 FPGA Integrated Endpoint Block v1.2 for PCI Express - Simulation failure when using ISE 11.5 to simulate a v1.2 core generated in ISE Design Suite 11.3 or 11.4, in 11.5

(Xilinx Answer 34451) - Spartan-6 FPGA Integrated Endpoint Block v1.2 rev 1 for PCI Express - Simulation never finishes when simulating a v1.2 rev 1 core generated in ISE Design Suite 11.5

Revision History
03/08/2010 - Updated for ISE 11.5; added 34341, 34451
01/20/2010 - Fixed incorrect reference from Virtex-6 to Spartan-6 under "General Information"
01/18/2010 - Added 34166
01/14/2010 - Added 34101
12/09/2009 - Added 33918
11/09/2009 - Added 33774
11/05/2009 - Added 33761
09/16/2009 - Initial Release