UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33278

Endpoint Block Plus Wrapper v1.12 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.3

Description


This Release Notes and Known Issues Answer Record is for the Endpoint Block Plus Wrapper v1.12, released in ISE Design Suite 11.3, and contains the following information:

- General Information
- New Features
- Bug Fixes
- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution


General Information

The LogiCORE Endpoint Block Plus for PCI Express is shipped with a free license. See (Xilinx Answer 33386) for more information.

The v1.12 core now includes source code for the Block Plus wrapper that instantiates the integrated block for PCI Express. The wrapper source code is contained in the directory named <project_name>/source. An ngc file is no longer delivered and the source code is synthesized as part of the user project. The synthesis scripts in the <project_name>/implement directory show examples of how to read in the source code for synthesis. Xilinx does not support any modifications made to the source code.

New Features

- ISE 11.3 software support
- Source Code release
- Configuration Write support (optional)

Resolved Issues

- CR 502953: Configuration Write Ability Enhancement
The Endpoint Block Plus Core now optionally supports Writes to the Configuration Registers in the Integrated Block for PCI Express through the Configuration Port. Please refer to the LogiCORE IP Endpoint Block Plus for PCI Express User Guide for further information on enabling and using this feature.

- CR 513853: Virtex-6 FPGA Integrated Block for PCI Express Root Port model for simulation.
The DS Port model in the simulation Testbench delivered with the Endpoint Block Plus Core has been replaced by the Virtex-6 FPGA Integrated Block for PCI Express Root Port model.

CR 510686: board.v contains incorrect work-around for 1-lane Verilog cores
The issue with the board.v containing an incorrect work-around for 1-lane Verilog cores has been resolved by replacement of the DS Port Model by the Virtex-6 FPGA Integrated Block for PCI Express Root Port model.

CR 517672: Extra Start-of-frame signal generated on Receive Transaction Interface
Issue resolved where the Virtex-5 FPGA Integrated Block Plus for PCI Express core generated an extra start-of-frame signal on the Transaction Receive interface (trn_rsof_n), without a corresponding end-of-frame (trn_reof_n) signal.

CR 525615: Core does not link-up when in a 2-lane configuration, on FXT / TXT devices
Issue resolved where the Virtex-5 FPGA Integrated Block Plus for PCI Express core did not link-up when in the 2-lane configuration on FXT/TXT devices. See (Xilinx Answer 33421).

CR 522894: Syntax error in x1 board_dual.v causes simulation failures
Issue resolved where comma missing from end of line 162 in board_dual.v.

CR 521843: MAP fails to complete due to predictable IP placement constraint issue
Issue resolved where naming of module instantiation interfered with predictable IP constraints.

CR 506202: DSPORT drops completions with Byte Count field 64 or larger
The v1.12 release replaces the downstream port with the new Virtex-6 FPGA Integrated Block for PCI Express Root Port model.

Known Issues
There are three main components to the Endpoint Block Plus Wrapper for PCI Express:

- Virtex-5 FPGA Integrated Block for PCI Express
- Virtex-5 FPGA GTP/GTX Transceivers
- Block Plus Wrapper FPGA fabric logic

The known issues for the integrated block and GTP/GTX transceivers are found in the Block Plus core user guide delivered with the core and found at:
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express_v5pciexpressblockplus.htm

Block Plus Wrapper FPGA fabric logic

(Xilinx Answer 31211) - Endpoint Block Plus Wrapper v1.12 for PCI Express - Link transitioning to L0s causes BAR settings to reset

(Xilinx Answer 31646) - Endpoint Block Plus Wrapper v1.12 for PCI Express - Dual Core UCF problems

(Xilinx Answer 31647) - Endpoint Block Plus Wrapper v1.12 for PCI Express - Dual core implement_dual.bat missing

(Xilinx Answer 31850) - Endpoint Block Plus Wrapper v1.12 for PCI Express - Simulation testbench writes to incorrect address for device control register

(Xilinx Answer 33400) - Endpoint Block Plus Wrapper v1.12 for PCI Express -ModelSim Simulation Results in Numerous Signals Trimmed from the Wave Dump

(Xilinx Answer 33401) - Endpoint Block Plus Wrapper v1.12 for PCI Express - ERROR:sim:159 - An internal error has occurred - when disabling TX_DIFF_BOOST

(Xilinx Answer 33410) - Endpoint Block Plus Wrapper v1.12 for PCI Express - Compatibility Issues with ISE Project Navigator Due to PIO_EP.v File Module Declarations and 64-bit interface ifdef declaration

(Xilinx Answer 33411) - Endpoint Block Plus Wrapper v1.12 for PCI Express - After Warm Reset, TX Direction Stalls Forever Due to Deassertion of trn_tdst_rdy_n

(Xilinx Answer 33534) - Endpoint Block Plus for PCI Express Wrapper v1.12 for PCI Express - Using Synplify with the Block Plus Wrapper Source Code Delivery

(Xilinx Answer 33643) - Endpoint Block Plus Wrapper v1.12 for PCI Express - Cannot implement the core in Project Navigator

(Xilinx Answer 33699) - Endpoint Block Plus Wrapper v1.12 for PCI Express - Polarity Reversal on Lane 7 Could Cause the Core Not to Train all 8 Lanes

(Xilinx Answer 33709) - Endpoint Block Plus Wrapper v1.12 for PCI Express - Improve Timing Closure

(Xilinx Answer 33710) - Endpoint Block Plus Wrapper v1.12 for PCI Express - Extended Deassertions of trn_rnp_ok_n Could Result in Completions Being Blocked Inside the Core

Revision History
10/23/2009 - Added 33643, 33699, 33709, 33710
09/22/2009 - Added AR 33411; Added 33421 link to Resolved Issue
09/18/2009 - Added 33534
09/16/2009 - Initial Release
AR# 33278
Date Created 09/09/2009
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • Endpoint Block Plus Wrapper for PCI Express