AR #33281 - Virtex-6 FPGA - Speed Files Revision History

AR#	33281
Topic	SW-Speedfiles
Last Modified	2009-11-10 00:00:00.0
Status	Active

Solution

Speeds Files Revision History

1.02 Release: Description and Explanation of Changes - 11.4
General Devices (LX/ LXT, SXT, and HXT devices)
+ Added HST -3 speed grade
+ Added default System Jitter values
+ PCIE - updated parameters
+ GTHE - updates to MINPERIOD/FMAX parameters
+ IOB - updates on the Datain2Dataout path - Moved a delay from IOB to IODELAY
+ DSP - updated parameters
+ MMCM - updated interconnects and cascaded components
+ IODELAY - Moved a delay from IOB to IODELAY
+ IOI and SERDES - Updated parameters
+ CLB - Updated setups on LUT RAM and slow down LUT delays
+ System Monitor - updated parameters

CXT Devices (1.03)
+ Added default System Jitter values
+ IOB - updates on the Datain2Dataout path - Moved a delay from IOB to IODELAY
+ DSP - updated parameters
+ MMCM - updated interconnects and cascaded components
+ IODELAY - Moved a delay from IOB to IODELAY
+ IOI and SERDES - Updated parameters
+ CLB - Updated setups on LUT RAM and slow down LUT delays
+ System Monitor - updated parameters

LP Devices
+ Added default System Jitter values
+ IOB - updates on the Datain2Dataout path - Moved a delay from IOB to IODELAY
+ DSP - updated parameters
+ MMCM - updated interconnects and cascaded components
+ IODELAY - Moved a delay from IOB to IODELAY
+ IOI & SERDES - Updated parameters
+ CLB - Updated setups on LUT RAM and slow down LUT delays
+ System Monitor - updated parameters

1.01 Release: Description and Explanation of Changes - 11.3
General Devices (LX / LXT and SXT devices)
+ Clocking - Updated BUFIO interconnect delays - Updated clocking values for HXT devices from confidence level 6 to 6.9
+ RAMB / FIFO - Updated minperiod checks depending if the site is configured as read_first, write_first or no_change
+ IODELAY - Increased ODATAIN -> DATAOUT between 172 ps and 269 ps depending on speed grade. - Updated uncertainty values for the first 6 tap values. Fastmax=Slowmax
+OLOGIC -Changed Fmax on D_OLOGICE1_OUTFF_CK_MINPERIOD from 924 MHz to (665 MHz - 739 MHz) depending on speed grade.
+ DSP48E1 - Added new parameters for CEA1 and CEB1 setup and hold checks to AREG_2 and BREG_2 respectively
+ IOI - Added new speed models for _{L,R}IOI_DATAOUT2D (requires a device modeling update)
+ GTHE1_QUAD - Just about delay values (setup / hold and clk -> out) value changed. - Confidence level moved from 1.0 to 6.9 on all values except for REFCLK to TSTREFCLKOUT/FAB
+ TEMAC_SINGLE - CLK to EMACCLIENTTXACK/COLLISION/RETRANSMIT values decreased at the slow and fast corners for all speed grades. - Added timing arc parameters.
+ GTXE - Setup requirements to TXUSRCLK2 and RXUSRCLK2 decreased for -2 and -1 speed grades. Hold requirements did not change. - IOPath delays from TXUSERCLK2, RXUSRCLK2 and SCANCLK decreased at the slow corner. - DCLK to DRDY and DRPDO decreased at the slow corner for all speed grades. - MinPeriod values on DCLK increased at the slow corner for all speed grades. - NORTHREFCLKRX and MGTREFCLKRX to MGTREFCLKFAB moved from confidence level 9.0 to 1.0.
+ PCIe_2 - MinPeriod checks were added for USERCLK, PIPECLK, and DRPCLK. They were already in the speed file, but they are now added to the delaymodels.
+ MMCM - Lowered values for MMCM_CLKPFD_FREQ_MAX

CXT Devices (1.02)
+ Clocking - Updated BUFIO interconnect delays
+ DSP48E1- Changed due to CXT Marketing SPEEDLIMITS for various fast modes - Added new parameters for CEA1 and CEB1 setup and hold checks to AREG_2 and BREG_2 respectively
+ RAMB / FIFO - Changed due to CXT Marketing SPEEDLIMITS for various fast modes - Updated minperiod checks depending if the site is configured as read_first, write_first, or no_change
+ IODELAY - Updated uncertainty values for the first 6 tap values. Fastmax=Slowmax
+ OLOGIC - Changed Fmax on D_OLOGICE1_OUTFF_CK_MINPERIOD from 924 MHz to (665 MHz - 739 MHz) depending on speed grade.
+ IOI - Added new speed models for _{L,R}IOI_DATAOUT2D (requires a device modeling update)
+ GTHE1_QUAD - Just about delay values (setup / hold and clk -> out) value changed. - Confidence level moved from 1.0 to 6.9 on all values except for REFCLK to TSTREFCLKOUT/FAB
+ TEMAC_SINGLE - CLK to EMACCLIENTTXACK/COLLISION/RETRANSMIT values decreased at the slow and fast corners for all speed grades. - Added need timing arc parameters
+ GTXE - Setup requirements to TXUSRCLK2 and RXUSRCLK2 decreased for -2 and -1 speed grades. Hold requirements did not change. - IOPath delays from TXUSERCLK2, RXUSRCLK2 and SCANCLK decreased at the slow corner. - DCLK to DRDY and DRPDO decreased at the slow corner for all speed grades. - MinPeriod values on DCLK increased at the slow corner for all speed grades. - NORTHREFCLKRX and MGTREFCLKRX to MGTREFCLKFAB moved from confidence level 9.0 to 1.0.
+ PCIe_2 - MinPeriod checks were added for USERCLK, PIPECLK, and DRPCLK. They were already in the speed file, but they are now added to the delaymodels.
+ MMCM - Lowered values for MMCM_CLKPFD_FREQ_MAX

LP Devices
+ Clocking -Updated BUFIO interconnect delays
+ RAMB / FIFO - Updated minperiod checks depending if the site is configured as read_first, write_first or no_change - Added need timing arc parameters
+ IODELAY - Updated uncertainty values for the first 6 tap values. Fastmax=Slowmax - Updated a LEAKAGE adjustment. This reduces uncertainty per tap value on all designs.
+ CLB - corrected values for D_SL_DFF_DQ (now they are 0.000)
+ DSP48E1 - Added new parameters for CEA1 and CEB1 setup and hold checks to AREG_2 and BREG_2 respectively
+ IOI - Added new speed models for _{L,R}IOI_DATAOUT2D (requires a device modeling update)
+ TEMAC - Updated several parameters to change slowmin and slowmax delays.
+ GTHE1_QUAD - Just about delay values (setup / hold and clk -> out) value changed. - Confidence level moved from 1.0 to 6.9 on all values except for REFCLK to TSTREFCLKOUT/FAB
+ TEMAC_SINGLE - CLK to EMACCLIENTTXACK/COLLISION/RETRANSMIT values decreased at the slow and fast corners for all speed grades. - Added need timing arc parameters
+ GTXE - Setup requirements to TXUSRCLK2 and RXUSRCLK2 decreased for -2 and -1 speed grades. Hold requirements did not change. - IOPath delays from TXUSERCLK2, RXUSRCLK2 and SCANCLK decreased at the slow corner. - DCLK to DRDY and DRPDO decreased at the slow corner for all speed grades. - MinPeriod values on DCLK increased at the slow corner for all speed grades. - NORTHREFCLKRX and MGTREFCLKRX to MGTREFCLKFAB moved from confidence level 9.0 to 1.0.
+ PCIe_2 - MinPeriod checks were added for USERCLK, PIPECLK, and DRPCLK. They were already in the speed file, but they are now added to the delaymodels.
+ MMCM - Lowered values for MMCM_CLKPFD_FREQ_MAX