Spartan-6 FPGA - Speed Files Revision History

Description

This Answer Record contains the Revision History for Spartan-6 family speed files.

Solution

• IODELAY - Updated Parameters
• Clocking - Updated Parameters

• No Change

• Devices ASLX4 and ASLX9 for all speed grades are labeled as PRODUCTION
• Clocking - Updated Parameters
• PCI_LOGIC - Updated Parameters
• Interconnect - Updated Parameters
• BRAM - Updated Parameters
• CLB - Updated Parameters
• DCM - Updated Parameters
• DSP - Updated Parameters
• IOB - Updated Parameters
• IODELAY - Updated Parameters
• PCIE - Updated Parameters
• PLL - Updated Parameters

• No Change

• Clocking - Updated Parameters

• No Change

• Devices ASLX4 and ASLX9 for all speed grades are labeled as PRELIMINARY
• Clocking - Updated Parameters
• BRAM - Updated Parameters
• DCM - Updated Parameters
• IODELAY - Updated Parameters
• PLL - Updated Parameters
• CLB - Updated Parameters
• SERDES - Updated Parameters

• Clocking - Updated Parameters
• BRAM - Updated Parameters
• DCM - Updated Parameters
• IODELAY - Updated Parameters
• PLL - Updated Parameters
• CLB - Updated Parameters
• Jitter - Updated Parameters

• Clocking - Updated Parameters
• IOB - Updated Parameters
• DCM/PLL - Updated Parameters
• IODELAY - Updated Parameters
• GTP - Updated Parameters
• PCIe - Updated Parameters
• Devices LX4, LX9, and LX25t are labeled as PRELIMINARY
• Devices LX150/150t, LX100/100t, LX75/75t are labeled as PRODUCTION

• Same as General Devices
• Updated Removal and Recovery delays

• BRAM - Updated Parameters
• DCM - Updated Parameters
• PLL - Updated Parameters
• PCIe - Updated Parameters
• IODELAY - Updated Parameters

• Same as General Devices
• All -1L devices are labeled as ADVANCED

• MCB - Updated Parameters
• PCIe - Updated Parameters
• Clocking- Updated Parameters
• DCM/PLL- Updated Parameters
• IODELAY- Updated Parameters

• Same as General Devices

• IOB - Updated Parameters

• DSP - Updated Parameters and Fixed Negative Data Valid window issue
• IOB - Updated Parameters and Fixed Negative Data Valid window issue

• Label changed for LX45/45T -2 to PRELIMINARY
• PLL, DCM - Updated Parameters
• IOB - Updated Parameters
• IODELAY - Updated Parameters
• PCIe - Updated Parameters
• SERDES - Updated Parameters
• GTP - Update Parameters
• MC - Updated Parameters
• LP Devices
• GTP - Updated Parameters
• Added XQ Devices

• OLOGIC - Updated parameters
• MC - Updated Parameters and Component Switching Limit Checks
• PLL, IOB, DSP, SERDES - Updated Parameters

• PLL - Updated Component Switching Limit Checks

• PCIe, BRAM, CLB, DSP, IOB, IODELAY, PLL, and SERDES - Updated Parameters
• DCM - Updated Parameters and Component Switching Limit Checks
• GTP - Updated Parameters
• Added XQ Devices

• DSP - Updated setup/hold Parameters for -2 and -4
• PCIe - Updated Parameters
• IOB - Updated Parameters
• GTP - Updated Parameters

• Added Automotive Subfamily for -2 and -3 Speed Grades
• CLB - Updated Equations for MINPERIODs
• DSP - Updated MINPERIOD/FMAX for -2 and -3 Speed Grades
• IOB - Updated equations for MINPERIODs - updated -3 speed grade for ILOGIC/OLOGIC delays for simulation - Updated TFF delays for DDR
• IODELAY - Updated setup/hold for -3 and -4 speed grades
• SERDES - Updated setup/hold for -3 and -4 speed grades
• DCM - Updated Pulsewidth Parameters and Jitter Values
• GTP - Updated Parameters
• PCIe - Updated Derate Factors
• MCB - Updated Parameters

• Updates to the IODELAY, SERDES, DSP, GTP, and Clocking Components
• Fixed Negative Data Valid Window for Simulation
• DCM - Updated Pulsewidth Parameters and Jitter Values
• IOB - Updated TFF Delays for DDR
• DSP - Updated parameters
• CLB - Updated Equations for MINPERIOD
• GTP - Updated Parameters
• PCIe - Updated Derate Factors
• MCB - Updated Parameters

• Added Support for 6slx75(t)
• DCM - Updated DCM_OFFSET values. This makes the min bigger than the max (on purpose) to prevent negative setup and hold windows on downstream blocks.
• DSP - For existing paths that use OPMODE6 or generic OPMODEs that include B1REG, a pre-adder delay was added. - There were more parameters that were added to reduce the delay when the pre-adder is specifically turned off.
• Interconnect - Added new speed models for input path from pad to IOI.
• PLL - Updated PLL_OFFSET values. This makes the min bigger than the max (on purpose) to prevent negative setup and hold windows on downstream blocks. - Set system synchronous setting to tap value 0. This was based on silicon characterization.
• BRAM - Differentiated between setup/hold and recovery/removal checks when in synchronous and asynchronous reset mode.
• I/O/Clocking - Updated O_BUFIO2.drive from the matching clk tree simulations - Updates to I/O and clocking models BSW_IOBUF_MUX, BSW_TERM_CLK, BSW_TERM_CLK2 - Updated B_IOCLK_TB/LR for sa16 and sa45 - Updated BSW_REGC_CLK_MUX_2 from design
• Updated IOB, Clocking Components
• BRAM/DSP - Updated Input Pin Delays
• GTP - Added Data Sheet Parameters and MINPERIOD values for D_GTPA1_DUAL_{GCLK??,PLLCLK??}_REFCLKPLL
• PCIe - Updated Values for -3 speed grade
• SERDES - Updated Values