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AR# 33285

ModelSim - Fatal: (vsim-3483) Delay in signal assignment is not ascending


Keywords: ModelSim, fatal error, resolution

I receive the following error in ModelSim when running behavioral simulation:

# ** Fatal: (vsim-3483) Delay in signal assignment is not ascending.
# Time: 0 us Iteration: 0 Process: /t_keybd/uut1/spi_access_inst/line__1439 File: C:/03_Softwares/11_1/ISE/vhdl/src/unisims/primitive/SPI_ACCESS.vhd
# Fatal error in Architecture spi_access_v at C:/03_Softwares/11_1/ISE/vhdl/src/unisims/primitive/SPI_ACCESS.vhd line 1439

How do I fix it?


Xilinx HDL libraries are functionally verified with resolution time set to ps. So setting the resolution time to ps in Modelsim.ini file might resolve this issue. Or if you have created a project with ModelSim, make sure that the resolution is set to ps in the <project>.mpf file.

If you have further queries and if the solution does not help resolve the problem, please open a Xilinx Technical Support WebCase:
AR# 33285
Date Created 10/13/2009
Last Updated 10/13/2009
Status Active
Type General Article