MIG v3.2, Virtex-6 FPGA DDR2/3 - Calibration does not complete or completes incorrectly for x4 memory parts

AR#	33288	Search For Another Answer
Topic	MIG
Last Updated	06/13/2011
Status	Active

Description

There is an issue with the Virtex-6 FPGA DDR2/DDR3 read leveling algorithm, which affects ALL designs using x4 parts.

This causes problems in hardware where any nibble beyond DQS[0] either does not calibrate correctly, or does not finish calibration. This issue is seen in simulation only if calibration for all bytes is enabled (i.e., SIM_CAL_OPTION = "NONE").

Solution

This issue occurs as the read leveling logic is hard-coded for x8 parts.

This issue is be resolved in MIG 3.3, which is available with ISE Design Suite 11.4.