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AR# 33288

MIG v3.2, Virtex-6 FPGA DDR2/3 - Calibration does not complete or completes incorrectly for x4 memory parts

Description

There is an issue with the Virtex-6 FPGA DDR2/DDR3 read leveling algorithm, which affects ALL designs using x4 parts.

This causes problems in hardware where any nibble beyond DQS[0] either does not calibrate correctly, or does not finish calibration. This issue is seen in simulation onlyif calibration for all bytes is enabled (i.e., SIM_CAL_OPTION = "NONE").

Solution

This issue occurs as the read leveling logic is hard-coded for x8 parts.

This issue is be resolved in MIG 3.3, which is available with ISE Design Suite11.4.
AR# 33288
Date Created 09/09/2009
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG